CHAPTER 3 LCD CONTROLLER/DRIVER
User’s Manual U18438EJ2V0UD
20
3.3 Controlling LCD Controller/Driver
LCDCTL (control registers) and LCDSEG (display RAM) have the individual slave ID, and control registers and
display RAM have unique addresses. The target control registers and display RAM are accessed by I
2
C with these
slave ID and addresses.
Table 3-3. Slave ID and Address of LCDCTL and LCDSEG
Block
Control registers/Display RAM
Slave ID (7 bits)
Address (8 bits)
LCD mode setting register (LCDMD)
00000000
LCD display mode register (LCDM)
00000001
LCD clock control register (LCDC)
00000010
LCDCTL
(Control block)
0 1 1 1 0 0 0
LCD voltage boost control register 0 (VLCG0)
00000011
S0 to S35
00000000 to 00100011
LCDSEG
(Display block)
0 1 1 1 0 0 1
S36 to S39
Note
00100100 to 00100111
Note
64-pin product only.
Remark
For details of communications by I
2
C, see
CHAPTER 4 I
2
C COMMUNICATIONS
.