CHAPTER 5 ELECTRICAL SPECIFICATIONS
User’s Manual U18438EJ2V0UD
62
DC Characteristics
(T
A
=
−
40 to +85
°
C, 1.8 V
≤
LV
DD
≤
5.5 V, LV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V
≤
LV
DD
≤
5.5 V
15
mA
2.7 V
≤
LV
DD
< 4.0 V
3
mA
Output current, low
I
OL
SDA
1.8 V
≤
LV
DD
< 2.7 V
0.6
mA
2.7 V
≤
LV
DD
≤
5.5 V 0.7LV
DD
LV
DD
V
V
IH1
SCL,
SDA
1.8 V
≤
LV
DD
< 2.7 V 0.8LV
DD
LV
DD
V
2.7 V
≤
LV
DD
≤
5.5 V 0.8LV
DD
LV
DD
V
Input voltage, high
V
IH2
RESET,
LCLK
1.8 V
≤
LV
DD
< 2.7 V 0.85LV
DD
LV
DD
V
2.7 V
≤
LV
DD
≤
5.5 V
0
0.3LV
DD
V
V
IL1
SCL,
SDA
1.8 V
≤
LV
DD
< 2.7 V
0
0.2LV
DD
V
2.7 V
≤
LV
DD
≤
5.5 V
0.2LV
DD
V
Input voltage, low
V
IL2
RESET,
LCLK
1.8 V
≤
LV
DD
< 2.7 V
0.15LV
DD
V
I
OL
= 15 mA
2.0
V
I
OL
= 3 mA
4.0 V
≤
LV
DD
≤
5.5 V
0.4
V
I
OL
= 3 mA
0.6
V
I
OL
= 2 mA
2.7 V
≤
LV
DD
< 4.0 V
0.4
V
Output voltage, low
V
OL
SDA
I
OL
= 600
µ
A
1.8 V
≤
LV
DD
< 2.7 V
0.4
V
Input leakage current, high
I
LIH
V
I
= LV
DD
SCL, SDA, RESET, LCLK
3
µ
A
Input leakage current, low
I
LIL
V
I
= 0 V
SCL, SDA, RESET, LCLK
−
3
µ
A
Output leakage current, high I
LOH
V
O
= LV
DD
3
µ
A
Output leakage current, low
I
LOL
V
O
= 0 V
−
3
µ
A
LCLK pull-down resistor
R
LCLK
After
reset
10
30
100 k
Ω
LV
DD
= 5.0 V
±
10% 25 50
µ
A
I
DD1
When LCD (including
booster circuit) is stopped
and IIC is operating
LV
DD
= 3.0 V
±
10% 13 30
µ
A
LV
DD
= 5.0 V
±
10% 2 36
µ
A
I
DD2
When only LCD booster
circuit is operating and IIC
is in standby status
LV
DD
= 3.0 V
±
10% 1.5 16
µ
A
LV
DD
= 5.0 V
±
10% 5 45
µ
A
I
DD3
When LCD display is
operating (voltage
boosting method) and IIC
is in standby status
LV
DD
= 3.0 V
±
10% 4 22
µ
A
LV
DD
= 5.0 V
±
10% 0.1 5
µ
A
I
DD4
When LCD (including
booster circuit) is stopped
and IIC is in standby
status
LV
DD
= 3.0 V
±
10% 0.05 3
µ
A
LV
DD
= 5.0 V
±
10% 3.1 14
µ
A
Supply current
Note
I
DD5
When LCD display is
operating (resistance
division method) and IIC
is in standby status
LV
DD
= 3.0 V
±
10% 2.55 9
µ
A
Note
Total current flowing into the internal power supply (LV
DD
), including the input leakage current flowing when the
level of the input pin is fixed to LV
DD
or LV
SS
. The current flowing into the pull-up resistors of the I
2
C
communication pins is not included.