CHAPTER 3 LCD CONTROLLER/DRIVER
User’s Manual U18438EJ2V0UD
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(2) Resistance division method
• Operation flow for transition of reset status to display status in LCD controller/driver
<1> Release the reset status (RESET = High level).
Note
<2> Supply the clock (Input the clock to LCLK).
<3> Set to the internal voltage boosting method using MDSET0 and MDSET1 (bit 0 and 1 of LCDMD).
(MDSET0, MDSET1 = 0, 0: External resistance division method,
MDSET0, MDSET1 = 0, 1: Internal resistance division method)
<4> Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
<5> Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)).
<6> Set the LCD clock using LCD clock control register (LCDC).
<7> Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
<8> Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
Note
During reset, the internal pull-down resistor is connected to the LCLK pin.
Input the low level to LCLK pin in advance before a reset release, because the internal pull-down
resistor is automatically disconnected when a reset is released.
Caution When using the resistance division method, voltage boosting must be stopped (VLCON = 0).
Remark
The register can be set in 1-bit units because the I
2
C bus is used for setting.