CHAPTER 3 LCD CONTROLLER/DRIVER
User’s Manual U18438EJ2V0UD
26
3.5 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
Remark
For details of communications by I
2
C, see
CHAPTER 4 I
2
C COMMUNICATIONS
.
(1) Voltage boosting method
• Operation flow for transition of reset status to display status in LCD controller/driver
<1> Release the reset status (RESET = High level).
Note
<2> Supply the clock (Input the clock to LCLK).
<3> Set MDSET1 (bit 1 of LCDMD) to 1 to set the internal voltage boosting method
(initial setting: external resistance division method)
<4> Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
<5> Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)) (1/2 bias mode and static mode cannot be set).
<6> Set the LCD clock using LCD clock control register (LCDC).
<7> Set the voltage boost level and contrasts using LCD voltage boost control register 0 (VLCG0).
GAIN = 0: V
LC0
= 4.5 V, V
LC1
= 3 V, V
LC2
= 1.5 V
GAIN = 1: V
LC0
= 3 V, V
LC1
= 2 V, V
LC2
= 1 V
<8> Set VLCON (bit 5 of LCDM) to 1 to enable voltage boosting.
<9> Wait for voltage boost wait time (t
VAWAIT
) from setting of VLCON (see
CHAPTER 5 ELECTRICAL
SPECIFICATIONS
).
<10> Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
<11> Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
Note
During reset, the internal pull-down resistor is connected to the LCLK pin.
Input the low level to LCLK pin in advance before a reset release, because the internal pull-down
resistor is automatically disconnected when a reset is released.
Remark
The register can be set in 1-bit units because the I
2
C bus is used for setting.