NEC PlasmaSync PX-42VM1G, Service Manual

Page: 113 / 172

6-8
CIRCUIT DESCRIPTION
2-2. Frequency Y/C separation (PAL, PAL M, PAL N)
The VIDEO signal input entered in Q5201 is band-pass limited at FL5201. Compensation for the level and
frequency characteristics is then carried out at the AMP (Q5202/5203) at the latter stage. The resultant
output is processed for Y/C separation at the latter stage.
The C component is removed at Q5205 to Q5206 and the Y signal is output from Q5205 to IC5203. Q5207
is turned on when PAL M/N is received.
Q5208 is turned on when PAL is received.
The C component is extracted at Q5210 to Q5212 and the C signal is output from IC5205. Q5213 is turned
on when PAL M/N is received. (OFF in the case of PAL)
After passing through IC5204, the output of IC5203 (Signal Y) is processed for the frequency characteristic
compensation and peaking at Q5217 to Q5220. The resultant input is entered in IC5404 (for PAL/NTSC
process).
The output of IC5205 (Signal C) is entered in IC5404 (for PAL/NTSC process) and IC5408 (for SECAM
decoding).
2-3. PAL/NTSC decoding
After passing through the built-in delay line of IC5008, the Y signal is once output from Pin 4. This signal is
entered in Pin 15 of IC5403 (CTI) and amplified twice. Since then, the output is generated from Pin 2.
In the case of NTSC/PAL/SECAM, the signal passes through DL5401 and further IC5017 (SW circuit), and
is then returned to IC5008.
In the case of PAL M/N, the signal passes through DL5402 and further IC5017 (SW circuit), and is then
returned to IC5008.
After passing through the internal circuits of pedestal clamp, black expansion, DC reproduction, sharpness,
etc., the connections are extended to the internal RGB matrix circuit.
Signal Y input
Pin 15
IC5404 (NTSC/PAL
; TA1222)
DL5401
(DELAY LINE)
DL5402
(DELAY LINE)
IC5401
(UPD4066 ; SW)
IC5403
(TA8814 ; CTI)
Signal Y input
Pin 53
System discrimination is conducted for the C signal. If the system is intended for PAL or NTSC, the signal is
processed in the APC and ACC circuits and then treated for carrier reproduction and phase detection to
produce the R-Y/B-Y signal. The resultant signal is once output from Pins 5 and 6 of IC5404, and entered in
Pins 12 and 13 of IC5408 (SECAM decoding). After that, the signal passes through the internal SW, is
output from Pins 10 and 11, and fed to the next stage.
[For the system discrimination data, a control signal is output from Pins 3 and 7 of IC5404 in order to control
IC5408 (SECAM decoding) and IC5407 (1H DELAY).]
In IC5407 (1H DELAY), the signal is amplified and output from Pins 29 and 30. It is then entered in Pins 7
and 8 of IC5403 (CTI).
In IC5403, profile compensation is carried out for chroma signals and the output is generated from Pins 11
and 12. This output is returned to Pins 51 and 52 of IC5404.
In IC5404, internal color processing is carried out and the resultant operation is transferred to the RGB
matrix circuit.