6-5
CIRCUIT DESCRIPTION
(4)
Timing controller block (IC9004)
IC9004 is a timing controller used to generate a variety of timing pulses based on the entered sync
signal and clock inputs. IC9004 incorporates three systems of timing pulse generator circuits. Pins 211
to 239 are called System A, Pins 12 to 43 are called System B, and Pins 52 to 90 are called System C.
Each system offers the following functions:
System A: Pulses are generated and output to IC7503 (RGB
→
4:2:2 conversion) and IC7506 (I-P
conversion, profile emphasis). This operation is based mainly on the sync signal of the
input signal. According to the type of a signal, operation may be asynchronous in conjunc-
tion with the input. The clock input is selected by IC7503.
System B: Pulses are generated and output to the input side of IC8701 (auto-picture) and IC8503
(definition conversion), and also to Pin 6 of the HD connector and Pin 7 of the same con-
nector (component signal processor circuit). This operation is based on the sync signal and
clock of the input signal.
System C: Pulses are generated and output to the output side of IC8503 (definition conversion), and
also to IC9002 (ON-screen signal generation) and the plasma display module. The sync
signal used is the pulses generated in System A. The clock signal on the output side is
used.
In regard to the control of IC9004, refer to the previous Item 1. (10) g processor, ON-screen synthesis
processor block.
3. System control
IC9501 is a microcomputer for system control. In IC9501, various controls are carried out, such as input
signal changeover, A/D converter setting, provision of output signal timing from the timing controller, adjust-
ment of the video chroma block, selection of HD decoder hue, color density level, digital signal processing
method, control of the plasma display module, fault condition judgment in the set, and so on.
Pin 34 of the microcomputer IC9501 is a reset terminal that is connected to the reset IC (IC9505). This
terminal usually works at 5V.
Contents of controls are described below. The matters not described here are explained in the respective
circuit block descriptions.
(1)
Input signal discrimination
Based on the information of horizontal and vertical sync signals (Pins 7 and 8 of the MN connector) and
the data (Pins 1 to 4 of the HD connector) from the VIDEO PWB through the I2C bus, the microcom-
puter identifies the type of the input signal and performs various controls. During the entry of VIDEO3
input (with an input at Terminal S), the detection of S2 (automatic discrimination of the S terminal
system) is carried out. With a voltage at Pin 25, the screen size (screen mode) is automatically changed.
Voltage at Pin 25
Factors other than right
1.4~2.4V
3.5~5.0
Result of discrimination
4:3 (general)
4:3 (letter box)
16:9 (squeeze)
Screen size
By user selection
Zoom
Full
During the entry of RGB3 input, the presence of input signal is identified according to the condition at
the SCDT terminal (Pin 100; “H” in normal operation) and power management operation is carried out.
Summary of Contents for PlasmaSync PX-42VM1G
Page 10: ...NEC Technologies PlasmaSync Plasma Monitor User s Manual...
Page 118: ...METHOD OF DISASSEMBLY 7 1 1 Diagonal view of the main unit rear panel...
Page 134: ...MEMO...
Page 137: ...9 1 PACKAGING Packing details A Safety bracket SASSY B 1 Safety bag SASSY...
Page 139: ...D CUSHION CARTON BOX 9 3 PACKAGING...
Page 141: ...9 5 PACKAGING F CARTON BOX OUT...
Page 147: ...CONNECTION DIAGRAMS 11 1...
Page 148: ...BLOCK DIAGRAMS 12 1 MAIN PWB BLOCK...
Page 149: ...BLOCK DIAGRAMS 12 2 VIDEO BLOCK...
Page 150: ...BLOCK DIAGRAMS 12 3 AUDIO BLOCK...
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