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CHAPTER 19 INTERRUPT FUNCTIONS
Preliminary User’s Manual U14581EJ3V0UM00
(3) Priority specify flag registers (PR0L, PR0H, PR1L)
The priority specify flag registers are used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 19-4. Priority Specify Flag Register (PR0L, PR0H, PR1L) Format
Address: FFE8H After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PR0L
PPR1
PPR0
TMPR02
TMPR01
TMPR00
OVFPR
ADPR
WDTPR
Address: FFE9H After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PR0H
TMPR3
TMPR2
TMPR1
STPR
SRPR
SERPR
CSIPR3
PPR2
Address: FFEAH After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
PR1L
1
1
1
1
1
WTPR
WTIPR
CSIPR2
XXPRX
Priority Level Selection
0
High priority level
1
Low priority level
Cautions 1. When the watchdog timer is used in the watchdog timer mode 1, set 1 in the WDTPR flag.
2. Bits 3 to 7 of PR1L must be set to 1.
Summary of Contents for mPD780852 Series
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