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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U14581EJ3V0UM00
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-9. Stack Pointer Configuration
SP
15
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented prior to write (save) to the stack memory and is incremented after read (restore) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Caution
Since RESET input makes SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-10. Data to Be Saved to Stack Memory
Interrupt and
BRK instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair, low
SP SP _ 2
SP _ 2
Register pair, high
CALL, CALLF, and
CALLT instructions
PUSH rp instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Figure 3-11. Data to Be Reset from Stack Memory
RETI and RETB
instructions
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Register pair, low
SP SP + 2
SP
Register pair, high
RET instruction
POP rp instruction
SP + 1
PC7 to PC0
SP SP + 2
SP
SP + 1
SP + 2
SP
SP + 1
SP SP + 3
Summary of Contents for mPD780852 Series
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