NEC mPD780852 Series, Preliminary User'S Manual

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Preliminary User’s Manual U14581EJ3V0UM00
LIST OF FIGURES (4/5)
Figure No. Title Page
17-1 Sound Generator Block Diagram ...................................................................................................... 223
17-2 Concept of Basic Cycle Output Signal SGO ..................................................................................... 223
17-3 Sound Generator Control Register (SGCR) Format ......................................................................... 226
17-4 Sound Generator Buzzer Control Register (SGBR) Format ............................................................. 227
17-5 Sound Generator Amplitude Register (SGAM) Format ..................................................................... 228
17-6 Sound Generator Output Operation Timing ...................................................................................... 229
18-1 Meter Controller/Driver Block Diagram ............................................................................................. 231
18-2 1-Bit Addition Circuit Block Diagram ................................................................................................. 232
18-3 Timer Mode Control Register (MCNTC) Format ............................................................................... 234
18-4 Compare Control Register n (MCMPCn) Format .............................................................................. 235
18-5 Port Mode Control Register (PMC) Format ...................................................................................... 236
18-6 Restart Timing after Count Stop (Count Start
→
Count Stop
→
Count Start) ...................................... 237
18-7 Timing in 1-Bit Addition Circuit Operation ......................................................................................... 238
18-8 Timing of Output with 1 Clock Shifted ............................................................................................... 239
19-1 Basic Configuration of Interrupt Function ......................................................................................... 243
19-2 Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format .............................................................. 246
19-3 Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format ............................................................ 247
19-4 Priority Specify Flag Register (PR0L, PR0H, PR1L) Format ............................................................ 248
19-5 External Interrupt Rising Edge Enable Register (EGP) and
External Interrupt Falling Edge Enable Register (EGN) Format ....................................................... 249
19-6 Prescaler Mode Register (PRM0) Format ........................................................................................ 250
19-7 Program Status Word Format ........................................................................................................... 251
19-8 Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................ 253
19-9 Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 253
19-10 Non-Maskable Interrupt Request Acknowledge Operation ............................................................... 254
19-11 Interrupt Request Acknowledge Processing Algorithm ..................................................................... 256
19-12 Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 257
19-13 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 257
19-14 Multiple Interrupt Examples .............................................................................................................. 259
19-15 Interrupt Request Hold ...................................................................................................................... 261
20-1 Oscillation Stabilization Time Select Register (OSTS) Format ......................................................... 264
20-2 HALT Mode Clear upon Interrupt Generation ................................................................................... 266
20-3 HALT Mode Clear upon RESET Input .............................................................................................. 267
20-4 STOP Mode Clear upon Interrupt Generation .................................................................................. 269
20-5 STOP Mode Clear upon RESET Input .............................................................................................. 270
21-1 Reset Function Block Diagram ......................................................................................................... 271
21-2 Timing of Reset by RESET Input ...................................................................................................... 272
21-3 Timing of Reset due to Watchdog Timer Overflow ........................................................................... 272
21-4 Timing of Reset in STOP Mode by RESET Input .............................................................................. 272