NEC mPD780852 Series, Preliminary User'S Manual

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U14581EJ3V0UM00
3.2.2 General registers
General registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. Four banks of
general registers, each consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H) are available.
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register
(AX, BC, DE, and HL).
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names
(R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupt processing for each bank.
Figure 3-12. General Register Configuration
(a) Absolute Name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing 8-bit processing
FEF0H
FEE8H
(b) Function Name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FEF0H
FEE8H