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CHAPTER 13 SERIAL INTERFACE UART
Preliminary User’s Manual U14581EJ3V0UM00
(2) Asynchronous serial interface status register (ASIS)
When a receive error occurs during UART mode, this register indicates the type of error.
ASIS is read with an 8-bit memory manipulation instruction.
RESET input clears ASIS to 00H.
Figure 13-3. Asynchronous Serial Interface Status Register (ASIS) Format
Address: FF86H After Reset: 00H R
Symbol
7
6
5
4
3
2
1
0
ASIS
0
0
0
0
0
PE
FE
OVE
PE
Parity Error Flag
0
No parity error
1
Parity error
(Transmit data parity does not match)
FE
Framing Error Flag
0
No framing error
1
Framing error
Note 1
(Stop bit not detected)
OVE
Overrun Error Flag
0
No overrun error
1
Overrun error
Note 2
(Next receive operation was completed before data was read from receive buffer register)
Notes 1. Even if a stop bit length of two bits has been set to bit 2 (SL) in the asynchronous serial interface
mode register (ASIM), stop bit detection during a receive operation only applies to a stop bit length
of 1 bit.
2. Be sure to read the contents of the receive buffer register (RXB) when an overrun error has
occurred.
Until the contents of RXB are read, further overrun errors will occur when receiving data.
(3) Baud rate generator control register (BRGC)
This register sets the serial clock for UART.
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Figure 13-4 shows the format of BRGC.
Summary of Contents for mPD780852 Series
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