NEC mPD780852 Series Preliminary User'S Manual Download

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CHAPTER 18 METER CONTROLLER/DRIVER

Preliminary User’s Manual U14581EJ3V0UM00

(2) Compare control register n (MCMPCn)

MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM

pin.

MCMPCn is set with an 8-bit memory manipulation instruction.

RESET input clears MCMPCn to 00H.

Figure 18-4 shows the MCMPCn format.

Figure 18-4. Compare Control Register n (MCMPCn) Format

Address: FF6BH to FF6EH After Reset: 00H R/W

Symbol

MCMPCn

TENn

ADBn1

ADBn0

DIRn1

DIRn0

TENn

Note

Transfer Enable Control Bit by Register from Master to Slave

Disables data transfer from master to slave.

New data can be written.

Transfers data from master to slave when MCNT overflows.

New data cannot be written.

ADBn1

1-Bit Addition Circuit Control (cos side of meter n)

No 1-bit addition to PWM output

1-bit addition to PWM output

ADBn0

1-Bit Addition Circuit Control (sin side of meter n)

No 1-bit addition to PWM output

1-bit addition to PWM output

DIRn1

DIRn0

Output Pin Control

SMn1

SMn2

SMn3

SMn4

PWM

Note TENn functions as a control bit and status flag.

As soon as the timer overflows and PWM data is output, TENn is cleared to “0” by hardware.

Caution

Bits 5 to 7 must be set to 0.

Remark n = 1 to 4

Summary of Contents for mPD780852 Series

Page 1: ...iminary User s Manual Printed in Japan PD780852 Subseries 8 Bit Single Chip Microcontrollers PD780851 A PD780852 A PD78F0852 Document No U14581EJ3V0UM00 3rd edition Date Published October 2000 J CP K...

Page 2: ...2 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 3: ...143 CHAPTER 11 CLOCK OUTPUT CONTROLLER 149 CHAPTER 12 A D CONVERTER 153 CHAPTER 13 SERIAL INTERFACE UART 169 CHAPTER 14 SERIAL INTERFACE SIO2 187 CHAPTER 15 SERIAL INTERFACE SIO3 201 CHAPTER 16 LCD C...

Page 4: ...nging description of supply voltage in 1 8 Outline of Function p 107 Changing 6 4 4 Port mode register 4 PM4 p 111 Changing Figure 6 11 Capture Register Data Retention Timing p 211 Adding Caution 3 to...

Page 5: ...ng bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touch...

Page 6: ...ties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge th...

Page 7: ...Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Ita...

Page 8: ...8 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 9: ...icrocontrollers To understand the functions of the PD780851 A 780852 A and 78F0852 in general Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number...

Page 10: ...801E Structured Assembly Language U11789J U11789E CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K0 C Compiler Application Note Programming Know how U13034J U13034E IE 78K0 N...

Page 11: ...r Device C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Se...

Page 12: ...12 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 13: ...Port 4 39 2 2 6 P50 to P54 Port 5 40 2 2 7 P60 P61 Port 6 40 2 2 8 P81 to P87 Port 8 41 2 2 9 P90 to P97 Port 9 41 2 2 10 COM0 to COM3 41 2 2 11 VLCD 41 2 2 12 AVREF 41 2 2 13 AVSS 41 2 2 14 RESET 41...

Page 14: ...73 CHAPTER 4 PORT FUNCTIONS 75 4 1 Port Functions 75 4 2 Port Configuration 77 4 2 1 Port 0 77 4 2 2 Port 1 78 4 2 3 Port 2 79 4 2 4 Port 3 80 4 2 5 Port 4 81 4 2 6 Port 5 82 4 2 7 Port 6 83 4 2 8 Po...

Page 15: ...8 3 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Control Registers 124 8 4 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Operations 128 8 4 1 8 bit interval timer operation 128 8 4 2 External event counte...

Page 16: ...ERIAL INTERFACE SIO2 187 14 1 Serial Interface Functions 187 14 2 Serial Interface Configuration 188 14 3 Serial Interface Control Registers 189 14 4 Serial Interface Operations 193 14 4 1 Operation s...

Page 17: ...ources and Configuration 241 19 3 Interrupt Function Control Registers 245 19 4 Interrupt Servicing Operations 252 19 4 1 Non maskable interrupt request acknowledge operation 252 19 4 2 Maskable inter...

Page 18: ...nstructions Listed by Addressing Type 292 APPENDIX A DEVELOPMENT TOOLS 297 A 1 Language Processing Software 299 A 2 Flash Memory Writing Tools 300 A 3 Debugging Tools 301 A 3 1 Hardware 301 A 3 2 Soft...

Page 19: ...Diagram 82 4 8 P60 and P61 Block Diagram 83 4 9 P81 to P87 Block Diagram 84 4 10 P90 to P97 Block Diagram 85 4 11 Port Mode Register PM0 PM4 to PM6 PM8 PM9 Format 87 4 12 Port Mode Register PM2 PM3 F...

Page 20: ...at 126 8 6 Port Mode Register 4 PM4 Format 127 8 7 Interval Timer Operation Timings 128 8 8 External Event Counter Operation Timings with Rising Edge Specified 131 8 9 PWM Output Operation Timing 133...

Page 21: ...terface SIO2 Block Diagram 187 14 2 Serial Operation Mode Register 2 CSIM2 Format 189 14 3 Serial Transfer Operation Timing According to CLPO and CLPH Settings 190 14 4 Serial Receive Data Buffer Stat...

Page 22: ...1L Format 247 19 4 Priority Specify Flag Register PR0L PR0H PR1L Format 248 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN Format 249 1...

Page 23: ...2 Internal Expansion RAM Size Switching Register IXS Format 277 22 3 Transmission Method Selection Format 278 22 4 Flashpro III Connection Using 3 Wire Serial I O Method SIO3 280 22 5 Flashpro III Co...

Page 24: ...tions 123 9 1 Interval Timer Interval Time 138 9 2 Watch Timer Configuration 138 9 3 Interval Timer Interval Time 140 10 1 Watchdog Timer Runaway Detection Time 144 10 2 Interval Time 144 10 3 Watchdo...

Page 25: ...Source List 242 19 2 Flags Corresponding to Interrupt Request Sources 245 19 3 Times from Generation of Maskable Interrupt Request until Servicing 255 19 4 Interrupt Request Enabled for Multiple Inter...

Page 26: ...26 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 27: ...pins that have an alternate function as segment signal output 8 bit resolution A D converter 5 channels Sound generator 1 channel Meter controller driver PWM output 8 bit resolution 16 Can set pulse...

Page 28: ...mory Remark indicates ROM code suffix 1 4 Quality Grade Part Number Package Quality Grade PD78F0852GC 8BT 80 pin plastic QFP 14 14 mm Standard PD780851GC A 8BT 80 pin plastic QFP 14 14 mm Special PD78...

Page 29: ...79 78 77 P90 S12 P91 S11 P92 S10 P86 S14 P87 S13 P93 S9 P94 S8 P95 S7 P96 S6 P97 S5 S4 S3 S2 S1 S0 COM3 COM2 COM1 COM0 V LCD 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29...

Page 30: ...ter Controller Power Supply P00 to P07 Port0 SMVSS Meter Controller Ground P10 to P14 Port1 SO2 SO3 Serial Output P20 to P27 Port2 TI00 to TI02 Timer Input P30 to P37 Port3 TIO2 TIO3 Timer Output Even...

Page 31: ...ion SIO of the PD78064 was enhanced and ROM and RAM were expanded EMI noise reduced version of the PD78064 Basic subseries for driving LCDs on chip UART PD780833Y 80 pin On chip J1850 CLASS2 controlle...

Page 32: ...16 K 1 ch UART 1 ch 33 Inverter PD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V Available control VFD PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V PD780232 16 K to 24...

Page 33: ...T LCD CONTROLLER DRIVER WATCH TIMER SERIAL INTERFACE SIO3 SCK3 P50 SO3 P51 SI3 P52 TxD P54 RxD P53 A D CONVERTER POWER FAIL DETECTOR ANI0 P10 to ANI4 P14 PCL TPO P60 SGO P61 AVSS AVREF SERIAL INTERFAC...

Page 34: ...output 16 CMOS input output 35 A D converter 8 bit resolution 5 channels Power fail detection function LCD controller driver Segment signal outputs 20 max Common signal outputs 4 max Bias 1 3 bias on...

Page 35: ...be specified in 1 bit units SI3 P53 RxD P54 TxD P60 Input Output Input PCL TPO P61 SGO P81 to P87 Input Output Input S19 to S13 P90 to P97 Input Output Port 9 Input S12 to S5 8 bit input output port...

Page 36: ...input to capture register CR02 P42 TIO2 Input Output 8 bit timer TM2 input output also used for 8 bit PWM output Input P43 TIO3 8 bit timer TM3 input output also used for 8 bit PWM output P44 TPO Outp...

Page 37: ...or output pin for power supply of pins other than port pins Connect this pin to VSS0 or VSS1 via a 0 1 F capacitor VSS1 Ground potential except for port block VPP High voltage application for program...

Page 38: ...ster 0 PU0 2 Control mode In this mode P00 to P07 function as external interrupt request input serial interface data input output and clock input output pins a INTP0 to INTP2 These are external interr...

Page 39: ...ation modes can be specified in 1 bit units 1 Port mode In this mode P30 to P37 function as an 8 bit output only port They go into a high impedance state when 1 is set to port mode register 3 PM3 2 Co...

Page 40: ...erial interface serial data output pin c SCK3 Serial interface serial clock input output pin d RxD TxD Asynchronous serial interface serial data input output pins 2 2 7 P60 P61 Port 6 These pins const...

Page 41: ...8 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 9 PM9 2 Control mode In this mode P90 to P97 function as segment signal output pins S5 to...

Page 42: ...potential pin except for port block 2 2 21 VPP PD78F0852 only A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified Di...

Page 43: ...utput Independently connect to VSS0 via a resistor P03 SCK2 P04 SO2 P05 SI2 P06 P07 P10 ANI0 to P14 ANI4 9 Input Independently connect to VDD0 or VSS0 via a resistor P20 SM11 to P23 SM14 4 Output Leav...

Page 44: ...ata output disable P ch IN OUT VDD N ch P ch VDD pullup enable Type 4 data output disable P ch OUT VDD N ch Type 8 A Type 8 Type 9 data output disable P ch IN OUT VDD N ch data output disable input en...

Page 45: ...Circuits of Pins 2 2 Type 17 Type 18 Type 17 G VLC0 VLC1 SEG data VLC2 P ch N ch P ch N ch P ch N ch OUT VLC0 VLC1 COM data VLC2 P ch N ch P ch N ch P ch N ch OUT N ch P ch VLC0 VLC1 SEG data VLC2 P...

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Page 47: ...registers 32 8 bits Internal ROM 32 768 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM...

Page 48: ...H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM 20 4 bits Reserved Program memory space A000H 9FFFH FA59H FA58H FA6D...

Page 49: ...H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM 20 4 bits Reserved Program memory space A000H 9FFFH FA59H FA58H FA6D...

Page 50: ...ng three areas are allocated to the program memory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area This area stores program start addresses to which execut...

Page 51: ...he 32 byte area FEE0H to FEFFH is allocated with four general purpose register banks composed of eight 8 bit registers The internal high speed RAM can be used as stack memory 2 LCD display RAM An LCD...

Page 52: ...particular special addressing methods designed for the functions of special function registers SFRs and general purpose registers are available for use Data memory addressing is illustrated in Figure...

Page 53: ...9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits SFR addressing...

Page 54: ...9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits SFR addressing...

Page 55: ...of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the p...

Page 56: ...and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Aux...

Page 57: ...es data as shown in Figures 3 10 and 3 11 Caution Since RESET input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 3 10 Data to Be Saved to Stack Memory I...

Page 58: ...X BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configurat...

Page 59: ...lation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand s...

Page 60: ...3 CR3 FF0DH 8 bit counter 1 TM1 R FF0EH 8 bit counter 2 TM2 FF0FH 8 bit counter 3 TM3 FF10H Capture register 00 CR00 0000H FF11H FF12H Capture register 01 CR01 FF13H FF14H Capture register 02 CR02 FF1...

Page 61: ...ister cos side MCMP11 FF63H Compare register sin side MCMP20 FF64H Compare register cos side MCMP21 FF65H Compare register sin side MCMP30 FF66H Compare register cos side MCMP31 FF67H Compare register...

Page 62: ...er LCDC FFE0H Interrupt request flag register 0L IF0 IF0L FFE1H Interrupt request flag register 0H IF0H FFE2H Interrupt request flag register 1L IF1L FFE4H Interrupt mask flag register 0L MK0 MK0L FFH...

Page 63: ...Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the...

Page 64: ...when the CALL addr16 BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to th...

Page 65: ...s executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Operation 15 1 15 0 PC 7 0 Low Addr High Addr Memory table...

Page 66: ...ng Instruction Register to be Specified by Implied Addressing MULU Register A for multiplicand and register AX for product storage DIVUW Register AX for dividend and quotient storage ADJBA ADJBS Regis...

Page 67: ...lowing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H...

Page 68: ...d with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr1...

Page 69: ...a capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective add...

Page 70: ...ces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfr...

Page 71: ...e register bank select flags RBS0 and RBS1 and the register pair specification code in the operation code This addressing can be carried out for all the memory spaces Operand format Identifier Descrip...

Page 72: ...Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 3 4 8 Based indexed addressing Function The B or C register contents specif...

Page 73: ...pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interru...

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Page 75: ...ty five input output port pins Figure 4 1 shows the port configuration Every port can be manipulated in 1 bit or 8 bit units controlled in various ways Moreover the port pins can also serve as I O pin...

Page 76: ...units SI3 P53 RxD P54 TxD P60 Input Output PCL TPO P61 SGO P81 to P87 Input Output S19 to S13 P90 to P97 Input Output Port 9 S12 to S5 8 bit input output port Input output mode can be specified in 1...

Page 77: ...be used in 1 bit units with a pull up resistor option register 0 PU0 Alternate functions include external interrupt request input serial interface data input output and clock input output RESET input...

Page 78: ...00 to P07 PM00 to PM07 Selector VDD0 Alternate functions Internal bus PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal 4 2 2 Port 1 Port 1 is a 5...

Page 79: ...nclude meter control PWM output RESET input sets port 2 to high impedance state Figure 4 4 shows a block diagram of port 2 Figure 4 4 P20 to P27 Block Diagram P20 SM11 to P23 SM14 P24 SM21 to P27 SM24...

Page 80: ...nclude meter control PWM output RESET input sets port 3 to high impedance state Figure 4 5 shows a block diagram of port 3 Figure 4 5 P30 to P37 Block Diagram P30 SM31 to P33 SM34 P34 SM41 to P37 SM44...

Page 81: ...s with the port mode register 4 PM4 Alternate functions also include timer input output RESET input sets port 4 to input mode Figure 4 6 shows a block diagram of port 4 Figure 4 6 P40 to P44 Block Dia...

Page 82: ...to input mode Figure 4 7 shows a block diagram of port 5 Caution When port 0 is used as the serial interface pins an I O and output latches must be set according to the functions to be used For an exp...

Page 83: ...units with the port mode register 6 PM6 Alternate functions include clock output and sound generator output RESET input sets port 6 to input mode Figure 4 8 shows a block diagram of port 6 Figure 4 8...

Page 84: ...so include segment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 8 to input mod...

Page 85: ...lso include segment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 9 to input mo...

Page 86: ...en a port pin is used as an alternate function pin set the port mode register and output latch corresponding to the port in accordance with the function to be used Cautions 1 Pins P10 to P17 are input...

Page 87: ...Symbol 7 6 5 4 3 2 1 0 PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 1 Address FF29H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PMmn Pmn Pin Input Output Mode Sele...

Page 88: ...n RESET input clears this register to 00H Caution When the on chip pull up resistor is used the pull up resistor is not cut off even when the port is set to the output mode To use the port in the outp...

Page 89: ...s the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read...

Page 90: ...90 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 91: ...lock Generator Block Diagram X1 X2 Main system clock oscillator HALFOSC fX Prescaler fX 2 fX 22 fX 23 fX 24 Prescaler Clock to peripheral hardware CPU clock fCPU Standby controller Selector STOP PCC2...

Page 92: ...PCC 0 0 0 0 0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 CPU Clock fCPU Selection 0 0 0 fX 0 0 1 fX 2 0 1 0 fX 22 0 1 1 fX 23 1 0 0 fX 24 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 Re...

Page 93: ...llator Mode Register OSCM Format Address FFA0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSCM HALFOSC 0 0 0 0 0 0 0 HALFOSC Oscillator Mode Selection 0 Normal operation mode 1 Reduced current consump...

Page 94: ...External clock X2 X1 IC Cautions 1 Do not execute the STOP instruction while an external clock is input This is because if the STOP instruction is executed the main system clock operation is stopped...

Page 95: ...of Resonator Connection 1 2 a Too long wiring b Crossed signal line X1 IC X2 X2 IC X1 PORTn n 0 to 6 8 and 9 c Wiring near high alternating current d Current flowing through ground line of oscillator...

Page 96: ...er s Manual U14581EJ3V0UM00 Figure 5 5 Incorrect Examples of Resonator Connection 2 2 e Signals are fetched IC X2 X1 5 4 2 Divider circuit The divider circuit divides the output of the main system clo...

Page 97: ...ed b Five types of CPU clocks 0 24 s 0 48 s 0 95 s 1 91 s and 3 81 s at 8 38 MHz operation can be selected by the PCC setting c Two standby modes STOP and HALT can be used d The clock to the periphera...

Page 98: ...5 3 Maximum Time Required for Switching CPU Clock Set Value after Switching PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0...

Page 99: ...ation The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the time during which oscillation stabilizes 217 fX is automat...

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Page 101: ...d 3 TM3 TM2 and TM3 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency and PWM see CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM...

Page 102: ...Interval timer 2 channels 1 channel 2 channels 1 channel Note 1 1 channel Note 2 mode External event counter Function Timer output PWM output Pulse width measurement Square wave output Divided output...

Page 103: ...S10 ES21 ES20 16 bit capture register CR01 16 bit capture register CR00 INTOVF INTTM02 INTTM01 INTTM00 ES21 ES20 ES11 fX 8 fX 16 fX 32 fX 64 ES10 ES01 CRC01 TMC02 TPOE CRC00 ES00 PRM01 PRM00 Prescaler...

Page 104: ...TMC02 2 Capture register 00 CR00 The valid edge of the TI00 pin can be selected as the capture trigger Setting of the TI00 valid edge is performed with the prescaler mode register PRM0 When the valid...

Page 105: ...on mode and controls the prescaler output signals TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC0 to 00H Figure 6 2 16 Bit Timer Mode Control Register TMC0 Fo...

Page 106: ...or 8 bit memory manipulation instruction RESET input clears CRC0 to 00H Figure 6 3 Capture Pulse Control Register CRC0 Format Address FF71H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CRC0 0 0 0 0 0 0...

Page 107: ...falling and rising edges PRM01 PRM00 Count Clock Selection 0 0 fX 23 0 1 fX 24 1 0 fX 25 1 1 fX 26 Caution Timer operation must be stopped before setting PRM0 Remarks 1 fX Main system clock oscillatio...

Page 108: ...s can be selected rising falling or both edges by means of bits 2 and 3 ES00 and ES01 of prescaler mode register PRM0 For TI00 pin valid edge detection sampling is performed at the count clock selecte...

Page 109: ...dge specified by bits 6 and 7 ES20 and ES21 of PRM0 is input to the TI02 P42 pin the value of TM0 is taken into 16 bit capture register 02 CR02 and external interrupt request signal INTTM02 is set Any...

Page 110: ...peration Timing by Free Running Counter with Both Edges Specified Count clock TM0 count value TI0m pin input Value loaded to CR0m INTTM0m TI0n pin input Value loaded to CR0n INTTM0n INTOVF D1 D0 t 100...

Page 111: ...ng 16 bit capture register 0n CR0n read CR0n performs capture operation but the capture value is not guaranteed However the interrupt request flag INTTM0n is set upon detection of the valid edge Figur...

Page 112: ...mer operation has been started TMC02 of TMC0 has been set to 1 with a high level applied to input pins TI00 to TI02 of 16 bit timer 0 and with the rising edge with ESn1 and ESn0 of PRM0 set to 0 1 or...

Page 113: ...8 bit interval timer Figure 7 1 shows timer 1 TM1 block diagram Figure 7 1 8 Bit Timer 1 TM1 Block Diagram Internal bus Internal bus 8 bit compare register 1 CR1 8 bit counter TM1 Clear Coincidence IN...

Page 114: ...t read only register which counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is...

Page 115: ...ion RESET input clears TCL1 to 00H Figure 7 2 Timer Clock Select Register 1 TCL1 Format Address FF73H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL1 0 0 0 0 0 TCL12 TCL11 TCL10 TCL12 TCL11 TCL10 Coun...

Page 116: ...t with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC1 to 00H Figure 7 3 8 Bit Timer Mode Control Register 1 TMC1 Format Address FF76H After Reset 00H R W Symbol 7 6 5 4 3 2 1...

Page 117: ...the TM1 can be selected with bits 0 to 2 TCL10 to TCL12 of the timer clock select register 1 TCL1 Setting 1 Set the registers TCL1 Select count clock CR1 Compare value 2 After TCE1 1 is set count oper...

Page 118: ...nterval Timer Operation Timings 2 3 b When CR1 00H t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time Interval time 00H 00H 00H 00H 00H c When CR1 FFH t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval t...

Page 119: ...eration Timings 3 3 d Operated by CR1 transition M N Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time 00H N N M N FFH 00H M 00H M CR1 transition TM1 overflows since M N e Operated by CR1 transition M...

Page 120: ...on If the values after the 8 bit compare register 1 CR1 is changed are smaller than the value of 8 bit timer register 1 TM1 TM1 continues counting overflows and then restarts counting from 0 Thus if t...

Page 121: ...k diagram and Figure 8 2 shows 8 bit timer event counter 3 TM3 block diagram Figure 8 1 8 Bit Timer Event Counter 2 TM2 Block Diagram Internal bus 8 bit compare register 2 CR2 8 bit counter 2 TM2 TIO2...

Page 122: ...r 3 CR3 8 bit counter 3 TM3 TIO3 P44 fX 212 fX 24 fX 26 Selector Coincidence Mask circuit OVF Clear 3 Selector TCL32 TCL31 TCL30 Timer clock select register 3 TCL3 Internal bus TCE3 TMC36 LVS3 LVR3 TM...

Page 123: ...sing edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H...

Page 124: ...TM3 TCL2 and TCL3 are set with an 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 8 3 Timer Clock Select Register 2 TCL2 Format Address FF74H After Reset 00H R W...

Page 125: ...other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 8 bit...

Page 126: ...nd start mode by matching between TMn and CRn 1 PWM Free running mode LVSn LVRn Timer Output F F Status Setting 0 0 No change 0 1 Timer output F F reset to 0 1 0 Timer output F F set to 1 1 1 Setting...

Page 127: ...pins as timer output pins clear the output latches of PM43 and PM44 and P43 and P44 to 0 PM4 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM4 to FFH Figure 8 6 Port M...

Page 128: ...timer register n TMn can be selected with the timer clock select register n TCLn Setting 1 Set the registers TCLn Select count clock CRn Compare value TMCn Select clear and start mode by match of TMn...

Page 129: ...V0UM00 Figure 8 7 Interval Timer Operation Timings 2 3 b When CRn 00H t Count clock TMn CRn TCEn INTTMn TIOn Interval time 00H 00H 00H 00H 00H c When CRn FFH t Count clock TMn CRn TCEn INTTMn TIOn 01...

Page 130: ...H N M 1 M 00H 01H M CRn transition Remark n 2 3 8 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TIOn TMn is incremented...

Page 131: ...eset to CRn by setting bit 0 TOEn of 8 bit timer mode control register n TMCn to 1 This enables a square wave with any selected frequency to be output duty 50 Setting 1 Set each register Set port latc...

Page 132: ...ic operation Setting 1 Set port latch P43 P44 and port mode register 4 PM43 PM44 to 0 2 Set active level width with 8 bit compare register CRn 3 Select count clock with timer clock select register n T...

Page 133: ...INTTMn TIOn 00H 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level ii CRn 0 Count clock TMn CRn TCEn INTTMn TIOn Inactive level Inactive level 01H 00H FFH 00H...

Page 134: ...ion N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H ii Change of CRn value to N to M after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn N N 1 N 2 FFH 00H 01H N N 1 N 2...

Page 135: ...ster change during timer count operation If the values after the 8 bit compare registers 2 and 3 CR2 and CR3 are changed are smaller than the value of 8 bit counters 2 and 3 TM2 and TM3 TM2 and TM3 co...

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Page 137: ...The watch timer and the interval timer can be used simultaneously Figure 9 1 shows watch timer block diagram Figure 9 1 Watch Timer Block Diagram 9 bit prescaler 5 bit counter Selector Selector Select...

Page 138: ...preset time interval Table 9 1 Interval Timer Interval Time Interval Time When Operated at fX 8 38 MHz 212 fX 489 s 213 fX 978 s 214 fX 1 96 ms 215 fX 3 91 ms 216 fX 7 82 ms 217 fX 15 65 ms Remark fX...

Page 139: ...7 WTM6 WTM5 WTM4 WTM3 0 WTM1 WTM0 WTM7 Watch Timer Count Clock Selection 0 fX 27 65 4 kHz 1 fX 211 4 09 kHz WTM6 WTM5 WTM4 Prescaler Interval Time Selection 0 0 0 24 fW 3 91 ms 0 0 1 25 fW 7 82 ms 0 1...

Page 140: ...WTM1 to 0 However since the 9 bit prescaler is not cleared the first overflow of the watch timer INTWT after zero second start may include an error of up to 29 1 fW 9 4 2 Interval timer operation The...

Page 141: ...imer Operation Timing 0H Start Overflow Overflow 5 bit counter Count clock fW or fW 29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interrupt time of watch timer 0 25 s Interval timer T...

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Page 143: ...the watchdog timer mode register WDTM Figure 10 1 shows the watchdog timer block diagram Figure 10 1 Watchdog Timer Block Diagram Prescaler INTWDT Maskable interrupt request INTWDT Non maskable interr...

Page 144: ...6 1 fX 7 82 ms 217 1 fX 15 6 ms 218 1 fX 31 3 ms 220 1 fX 125 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 Interval timer mode...

Page 145: ...sets overflow time of the watchdog timer and the interval timer WDCS is set with an 8 bit memory manipulation instruction RESET input clears WDCS to 00H Figure 10 2 Watchdog Timer Clock Select Regist...

Page 146: ...skable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow 1 1 Watchdog timer mode 2 Reset operation...

Page 147: ...the runaway detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value The watchdog timer is cleared if RUN is set to 1 The watchdog t...

Page 148: ...terval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction C...

Page 149: ...put controller block diagram Figure 11 1 Clock Output Controller Block Diagram fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 Selector Clock controller CLOE CCS2 CCS1 CCS0 PM60 PCL TPO P60 Clock output s...

Page 150: ...using a 1 bit memory manipulation instruction Figure 11 2 Clock Output Selection Register CKS Format Address FF40H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKS 0 0 0 CLOE 0 CCS2 CCS1 CCS0 CLOE PCL...

Page 151: ...in for clock output set PM60 and the output latch of P60 to 0 PM6 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM6 to FFH Figure 11 3 Port Mode Register 6 PM6 Format A...

Page 152: ...led status 3 Set the P60 output latch to 0 4 Set bit 0 PM60 of port mode register 6 to 0 set to output mode 5 Set bit 4 CLOE of CKS to 1 and enable clock output Caution The clock output cannot be used...

Page 153: ...olution One channel of analog input is selected from ANI0 to ANI4 and A D conversion is repeatedly executed with a resolution of 8 bits Each time the conversion has been completed interrupt request IN...

Page 154: ...t register ADCR1 Tap selector AVREF AVSS INTAD A D converter mode register ADM1 Analog input channel specification register ADS1 Internal bus ADS12 ADS11 ADS10 ADCS1 FR12 FR11 FR10 Series resistor str...

Page 155: ...t memory manipulation instruction RESET input clears ADCR1 to 00H Caution When write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the...

Page 156: ...A D converter is used It converts signals input to ANI0 to ANI4 into digital signals according to the voltage applied between AVREF and AVSS The current flowing in the series resistor string can be re...

Page 157: ...D Converter Mode Register ADM1 Format Address FF80H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADM1 ADCS1 0 FR12 FR11 FR10 0 0 0 ADCS1 A D Conversion Operation Control 0 Conversion operation stop 1 C...

Page 158: ...an 8 bit memory manipulation instruction RESET input clears ADS1 to 00H Figure 12 4 Analog Input Channel Specification Register ADS1 Format Address FF81H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 AD...

Page 159: ...Compare Mode Selection 0 ADCR1 PFT Generates interrupt request signal INTAD ADCR1 PFT Does not generate interrupt request signal INTAD 1 ADCR1 PFT Does not generate interrupt request signal INTAD ADCR...

Page 160: ...remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage...

Page 161: ...sion result A D conversion operations are performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input c...

Page 162: ...0 5 AVREF or ADCR1 0 5 AVREF VIN ADCR1 0 5 AVREF 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR1 A D conversion res...

Page 163: ...ion operation is immediately started A D conversion operations are repeated until new data is written to ADS1 If ADS1 is rewritten during A D conversion operation the A D conversion operation under ex...

Page 164: ...e 12 9 A D Conversion ADM1 rewrite ADCS1 1 ADS1 rewrite ADCS1 0 A D conversion ADCR1 INTAD PFEN 0 INTAD PFEN 1 ANIn ANIn ANIn ANIm ANIm Stop ANIn ANIn ANIm Conversion suspended Conversion results are...

Page 165: ...y instruction upon the end of conversion ADCR1 read is given priority After the read operation the new conversion result is written to ADCR1 2 Contention between ADCR1 write and A D converter mode reg...

Page 166: ...he analog input pins ANI0 to ANI4 also function as input port pins P10 to P14 When A D conversion is performed with any of pins ANI0 to ANI4 selected do not execute a port input instruction while conv...

Page 167: ...nge analog input has not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 12 12 A D Conversion End Interrupt Request Generatio...

Page 168: ...the power fail detection function Figure 12 13 D A Converter Mode Register DAM1 Format Address FF89H After Reset 00H W Symbol 7 6 5 4 3 2 1 0 DAM1 0 0 0 0 0 0 0 DACE DACE Reference Voltage Control 0...

Page 169: ...using a wide range of selectable baud rates For details see 13 4 2 Asynchronous serial interface UART mode Figure 13 1 shows the serial interface UART block diagram Figure 13 1 Serial Interface UART B...

Page 170: ...gned to TXS and the receive buffer register RXB A read operation reads values from RXB 2 Receive shift register RXS This register converts serial data input via the RxD pin to parallel data When one b...

Page 171: ...sed to control the serial interface UART Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Asynchronous se...

Page 172: ...e Serial function RxD Serial function TxD transmit and receive PS1 PS0 Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception pari...

Page 173: ...r Note 1 Stop bit not detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a...

Page 174: ...0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1...

Page 175: ...t function P53 Port function P54 0 1 UART mode Serial function RxD Port function P54 receive only 1 0 UART mode Port function P53 Serial function TxD transmit only 1 1 UART mode Serial function RxD Se...

Page 176: ...op Port function P53 Port function P54 0 1 UART mode Serial function RxD Port function P54 receive only 1 0 UART mode Port function P53 Serial function TxD transmit only 1 1 UART mode Serial function...

Page 177: ...framing error 1 Framing error Note 1 Stop bit not detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buff...

Page 178: ...for Baud Rate Generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK...

Page 179: ...g formula Baud rate fX Hz 2n 1 k 16 fX Main system clock oscillation frequency n Value set via TPS0 to TPS2 1 n 8 For details see Table 13 2 k Value set via MDL0 to MDL3 0 k 14 Table 13 2 shows the re...

Page 180: ...BH 1 10 1 200 6BH 1 10 2 400 5BH 1 10 4 800 4BH 1 10 9 600 3BH 1 10 19 200 2BH 1 3 31 250 21H 1 10 38 400 1BH 1 10 76 800 0BH 1 10 115 200 01H 1 03 Remark fX Main system clock oscillation frequency Fi...

Page 181: ...p bit s 1 bit or 2 bits The asynchronous serial interface mode register ASIM is used to set the character bit length parity selection and stop bit length within each data frame When 7 bits is selected...

Page 182: ...the receive data that include a parity bit and a parity error occurs when the result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit i...

Page 183: ...13 7 Figure 13 7 Asynchronous Serial Interface Transmit Completion Interrupt Timing TxD output D0 D1 D2 D6 D7 Parity STOP START INTST i Stop bit length 1 bit TxD output D0 D1 D2 D6 D7 Parity START INT...

Page 184: ...on of one data frame is completed the receive data in the shift register is transferred to the receive buffer register RXB and a receive completion interrupt INTSR occurs Even if an error has occurred...

Page 185: ...3 4 Causes of Receive Errors Receive Error Cause ASIS Value Parity error Parity specified during transmission does not match parity of receive data 04H Framing error Stop bit was not detected 02H Over...

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Page 187: ...first bit in the 8 bit data in serial transfer is fixed as the MSB This data contains a 1 byte receive buffer and can be received successively The serial clock and the data phase polarity can be selec...

Page 188: ...data is held in SIO2 RESET input clears SIO2 to 00H Cautions 1 Do not access read write SIO2 during a transmit receive operation shift operation 2 When a transmit receive operation starts writing to S...

Page 189: ...PH CLPO MODE2 SCL21 SCL20 CSIE2 SIO2 Operation Enable Disable Specification Shift Register Operation Serial Counter Port 0 Operation disabled Clear Port function 1 Operation enabled Counter operation...

Page 190: ...execute an access that will be the start trigger of each transfer operation mode 4 Changing CSIE2 and other bits at the same time is prohibited After clearing CSIE2 to 0 change the other bits Remark...

Page 191: ...tions 1 When an overflow error occurs receive data in SIO2 will not be transferred to SIRB2 even if the next receive operation for SIO2 is complete 2 When an overflow error occurs be sure to read SRBS...

Page 192: ...t FFH R W Symbol 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n Pin Input Output Mode Selection 0 Output mode output buffer on 1 Input mode output buffer off Remark n 0 to 7 Tabl...

Page 193: ...ins can be used as normal I O port pins 1 Register setting The operation stop mode is set with the serial operation mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruc...

Page 194: ...SCL21 SCL20 CSIE2 SIO2 Operation Enable Disable Specification Shift Register Operation Serial Counter Port 0 Operation disabled Clear Port function 1 Operation enabled Counter operation enabled Serial...

Page 195: ...fX Main system clock oscillation frequency 2 Communication operations Data is transmitted received in 8 bit units 8 bit data is transmitted received bit by bit in synchronization with the serial cloc...

Page 196: ...e the SCK2 pin operates as an external serial clock input pin Serial data is transferred to SIO2 in synchronization with the externally input serial clock After the serial data has been received by SI...

Page 197: ...0 Figure 14 6 shows the operation timing when CLPH 0 Two waves of SCK2 when CLPO 0 and when CLPO 1 are shown in the figure Data is transmitted or received in 8 bit units Each bit of data is transmitt...

Page 198: ...l input data AAH ABH 56H ADH 5AH B5H 6AH D5H AAH AAH AAH 55H SCK2 CLPO 0 SIRB2 SI2 SO2 SCK2 CLPO 1 55H Write SIO2 55H Serial output data timing Start trigger operation timing INTCSI2 interrupt request...

Page 199: ...read 4 SRBS2 is read and the status is checked overflow error check 5 Like 1 above DATA2 receive data is transferred to SIRB2 after it is received completely 6 Even though DATA3 receive data receptio...

Page 200: ...e In the HALT mode the CPU cannot access the registers of serial interface SIO2 If it is not necessary to use serial interface SIO2 in the HALT mode the power consumption can be reduced by stopping th...

Page 201: ...ive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is...

Page 202: ...and serial transmit receive shift operations synchronized with the serial clock SIO3 is set with an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE3 of the serial operation mode regi...

Page 203: ...3 to the output mode PM50 0 When serial clock input Slave transmit or slave receive Set P50 to the input mode PM50 1 When transmit or transmit receive mode Set P51 SO3 to the output mode PM51 0 When r...

Page 204: ...the P50 SCK3 P51 SO3 and P52 SI3 pins can be used as normal I O port pins 1 Register settings Operation stop mode is set with the serial operation mode register 3 CSIM3 CSIM3 is set with a 1 bit or 8...

Page 205: ...ows Besides that set all output latches to 0 When serial clock output Master transmit or master receive Set P50 SCK3 to the output mode PM50 0 When serial clock input Slave transmit or slave receive S...

Page 206: ...Timing SI3 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 CSIIF3 SCK3 1 SO3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronized with the falling edge of SCK3 3 Transfer...

Page 207: ...y of four frame frequencies can be selected in each display mode 4 Maximum of 20 segment signal outputs S0 to S19 4 common signal outputs COM0 to COM3 Fifteen of the segment signal outputs can be swit...

Page 208: ...to COM3 Control registers LCD display mode register LCDM LCD display control register LCDC Figure 16 1 LCD Controller Driver Block Diagram Note Segment driver Internal bus FA59H 7 6 5 4 3 2 1 0 FA67H...

Page 209: ...User s Manual U14581EJ3V0UM00 Figure 16 2 LCD Clock Selector Block Diagram Prescaler fLCD 2 3 fX 2 14 fLCD 2 2 fLCD 2 fLCD Selector LCDM6 LCDM5 LCDM4 3 LCDCL LCD display mode register Internal bus Rem...

Page 210: ...rame frequency LCDM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears LCDM to 00H Figure 16 3 LCD Display Mode Register LCDM Format Address FFB0H After Reset 00H R W Symb...

Page 211: ...LCDC7 LCDC6 LCDC5 LCDC4 P81 S19 to P97 S5 Pin Functions Port Pins Segment Pins 0 0 0 0 P81 to P97 None 0 0 0 1 P81 to P95 S5 S6 0 0 1 0 P81 to P93 S5 to S8 0 0 1 1 P81 to P91 S5 to S10 0 1 0 0 P81 to...

Page 212: ...ver settings should be performed as shown below 1 Set the initial value in the display data memory FA59H to FA6CH 2 Set the pins to be used as segment outputs in the LCD display control register LCDC...

Page 213: ...16 5 shows the relation between the LCD display data memory contents and the segment outputs common outputs Any area not used for display can be used as normal RAM Figure 16 5 Relation between LCD Di...

Page 214: ...y and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is converted to the non selection voltage and output to a segment pin S0 to S19 S18 to S5 ha...

Page 215: ...n signal and segment signal voltages and phases Figure 16 6 Common Signal Waveform TF 4 T COMn Divided by 4 VLC0 VSS VLCD VLC1 VLC2 T One LCDCL cycle TF Frame frequency Figure 16 7 Common Signal and S...

Page 216: ...is fixed to 1 3 bias To supply various LCD drive voltages internal VDD or external VLCD supply voltage can be selected Table 16 5 LCD Drive Voltage Bias Method 1 3 Bias Method LCD Drive Voltage VLC0...

Page 217: ...Connection of LCD Drive Power Supply a To supply LCD drive voltage from VDD VDD VSS VLCD VDD P ch LIPS 1 R R R VSS VLC2 VLC1 VLC0 VLCD Open VLCD pin b To supply LCD drive voltage from external source...

Page 218: ...es must be output to pins S8 and S9 as shown in Table 16 6 at the COM0 to COM3 common signal timings Table 16 6 Selection and Non Selection Voltages COM0 to COM3 Segment S8 S9 Common COM0 S S COM1 NS...

Page 219: ...COM3 COM2 COM1 COM0 BIT0 BIT1 BIT2 BIT3 S0 S1 S2 S3 1 1 0 FA6CH 1 1 1 B 1 1 0 A 1 0 0 9 S4 S5 S6 S7 1 1 0 8 1 1 1 7 1 1 0 6 1 0 0 5 S8 S9 S10 S11 1 1 0 4 1 1 1 3 1 1 0 2 1 0 1 1 S12 S13 S14 S15 0 1 0...

Page 220: ...M00 Figure 16 11 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method TF VLC0 VLC2 COM0 VLCD 0 COM0 to S8 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2...

Page 221: ...when using the LCD controller driver Figure 16 12 LCD Timer Control Register LCDTM Format Address FF4AH After Reset 00H W Symbol 7 6 5 4 3 2 1 0 LCDTM 0 0 0 0 0 0 TMC21 0 TMC21 LCD Clock Supply Contr...

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Page 223: ...n be varied to enable control of the buzzer sound volume Figure 17 1 shows the sound generator block diagram and Figure 17 2 shows the concept of basic cycle output signal SGO Figure 17 1 Sound Genera...

Page 224: ...ration The sound generator consists of the following hardware Table 17 1 Sound Generator Configuration Item Configuration Counter 8 bits 1 5 bits 1 SG output SGO Control register Sound generator contr...

Page 225: ...nd generator buzzer control register SGBR Sound generator amplitude register SGAM 1 Sound generator control register SGCR SGCR is a register which sets up the following three types Controls sound gene...

Page 226: ...G1 fX 2 1 fSG1 fX Cautions 1 Before setting the TCE bit set all the other bits 2 When rewriting SGCR to other data stop the timer operation TCE 0 beforehand 3 Bits 4 to 6 must be set to 0 4 Bit 3 must...

Page 227: ...X 8 38 MHz 0 0 0 0 3 677 3 851 0 0 0 1 3 472 3 637 0 0 1 0 3 290 3 446 0 0 1 1 3 125 3 273 0 1 0 0 2 976 3 117 0 1 0 1 2 841 2 976 0 1 1 0 2 717 2 847 0 1 1 1 2 604 2 728 1 0 0 0 2 500 2 619 1 0 0 1 2...

Page 228: ...0 0 1 0 0 1 10 128 0 0 0 1 0 1 0 11 128 0 0 0 1 0 1 1 12 128 0 0 0 1 1 0 0 13 128 0 0 0 1 1 0 1 14 128 0 0 0 1 1 1 0 15 128 0 0 0 1 1 1 1 16 128 0 0 1 0 0 0 0 17 128 0 0 1 0 0 0 1 18 128 0 0 1 0 0 1...

Page 229: ...n if the bit 7 TCE of the sound generator control register SGCR is set to 1 The basic cycle signal of the frequency set by SGCL0 to SGCL2 and SGBR0 to SGBR3 is output The amplitude of the basic cycle...

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Page 231: ...shows the block diagram of the meter controller driver and Figure 18 2 shows 1 bit addition circuit block diagram Figure 18 1 Meter Controller Driver Block Diagram Remark n 1 to 4 Internal bus Compar...

Page 232: ...ntrol register PMC Pulse controller 1 bit addition circuit output controller Remark n 1 to 4 1 Free running up counter MCNT MCNT is an 8 bit free running up counter and is a register that executes inc...

Page 233: ...r n is generated 4 1 bit addition circuit The 1 bit addition circuit repeats 1 bit addition non addition to PWM output alternately upon MCNT overflow output and enables the state of PWM output between...

Page 234: ...that controls the operation of the free running up counter MCNT MCNTC is set with an 8 bit memory manipulation instruction RESET input clears MCNTC to 00H Figure 18 3 shows the MCNTC format Figure 18...

Page 235: ...ontrol Bit by Register from Master to Slave 0 Disables data transfer from master to slave New data can be written 1 Transfers data from master to slave when MCNT overflows New data cannot be written A...

Page 236: ...put pins is shown below ENn MODn DIRn1 DIRn0 SMn1 SMn2 SMn3 SMn4 Mode sin sin cos cos 0 Port Port Port Port Port mode 1 0 0 0 PWM 0 PWM 0 PWM mode full bridge 1 0 0 1 PWM 0 0 PWM 1 0 1 0 0 PWM 0 PWM 1...

Page 237: ...Figure 18 6 shows the timing from count start to restart Figure 18 6 Restart Timing after Count Stop Count Start Count Stop Count Start CLK MCNT PCE 0H 1H 2H 1H 2H 3H 4H N N 1 00H Count start Count s...

Page 238: ...enables the state of PWM output between current compare value N and the next compare value N 1 In this mode 1 bit addition to the PWM output is set by setting ADBn of the MCMPCn register to 1 and 1 bi...

Page 239: ...er 1 sin SM11 SM12 Meter 1 cos SM13 SM14 Meter 2 sin SM21 SM22 Meter 2 cos SM23 SM24 Meter 3 sin SM31 SM32 Meter 3 cos SM33 SM34 Meter 4 sin SM41 SM42 Meter 4 cos SM43 SM44 If the wave of sin and cos...

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Page 241: ...d a low interrupt priority group by setting the priority specify flag registers PR0L PR0H PR1L High priority interrupts can be issued even if there are low priority interrupts If two or more interrupt...

Page 242: ...face SIO3 transfer Internal 0016H B 10 INTSER Generation of serial interface UART receive error 0018H 11 INTSR End of serial interface UART reception 001AH 12 INTST End of serial interface UART transm...

Page 243: ...le address generator Standby release signal B Internal maskable interrupt Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal C Ext...

Page 244: ...E PR ISP Internal bus Interrupt request Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector E Software interrupt Int...

Page 245: ...request sources Table 19 2 Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT WDTIF I...

Page 246: ...ation instruction RESET input clears these registers to 00H Figure 19 2 Interrupt Request Flag Register IF0L IF0H IF1L Format Address FFE0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L PIF1 PIF0 TM...

Page 247: ...PMK1 PMK0 TMMK02 TMMK01 TMMK00 OVFMK ADMK WDTMK Address FFE5H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK3 TMMK2 TMMK1 STMK SRMK SERMK CSIMK3 PMK2 Address FFE6H After Reset FFH R W Symbol 7 6...

Page 248: ...ion RESET input sets these registers to FFH Figure 19 4 Priority Specify Flag Register PR0L PR0H PR1L Format Address FFE8H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L PPR1 PPR0 TMPR02 TMPR01 TMPR0...

Page 249: ...anipulation instruction RESET input clears these registers to 00H Figure 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN Format Address...

Page 250: ...S21 ES20 ES11 ES10 ES01 ES00 PRM01 PRM00 ES21 ES20 TI02 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Interrupt disabled 1 1 Both rising and falling edges ES11 ES10 TI01 Valid Edge Selecti...

Page 251: ...ved into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag T...

Page 252: ...new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program...

Page 253: ...m CPU processing WDTIF Interrupt request generated during this interval is acknowledged at WDTIF Watchdog timer interrupt request flag Start WDTM4 1 with watchdog timer mode selected Overflow in WDT W...

Page 254: ...on of NMI request 1 NMI request 2 held pending Servicing of NMI request 2 that was pended b If two non maskable interrupt requests are generated during non maskable interrupt servicing program executi...

Page 255: ...ks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable inter...

Page 256: ...terrupt servicing Start IF 1 MK 0 PR 0 IE 1 ISP 1 Interrupt request held pending Yes Yes No No Yes Interrupt request generation Yes No Low priority No No Yes Yes No IE 1 No Any high priority interrupt...

Page 257: ...the contents are saved into the stacks in the order of the program status word PSW then program counter PC the IE flag is reset to 0 and the contents of the vector table 003EH 003FH are loaded into PC...

Page 258: ...rrently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because of the interrupt disable state or...

Page 259: ...the EI instruction must always be issued to enable interrupt request acknowledge Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy ser...

Page 260: ...EI 1 instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 Interrupt is not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not...

Page 261: ...PR1L PR1H EGP and EGN registers Caution The BRK instruction is not one of the above listed interrupt request hold instruction However the software interrupt activated by executing the BRK instruction...

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Page 263: ...memory low voltage hold down to VDD 2 0 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt r...

Page 264: ...5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation Stabilization Time Selection When STOP Mode Is Cleared 0 0 0 212 fX 488 s 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216...

Page 265: ...w Table 20 1 HALT Mode Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Item Clock generator Main system clock can be oscillated Clock supply to CPU stops C...

Page 266: ...ecuted Figure 20 2 HALT Mode Clear upon Interrupt Generation HALT instruction Wait Wait Operation mode HALT mode Operation mode Oscillation Clock Standby release signal Remarks 1 The broken line indic...

Page 267: ...cillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz Table 20 2 Oper...

Page 268: ...ter execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operation mode is set The operating status in the STOP mode is described belo...

Page 269: ...of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Gen...

Page 270: ...mode STOP mode Operation mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation...

Page 271: ...ilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset a...

Page 272: ...of Reset due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal r...

Page 273: ...ntrol register PCC 04H Memory size switching register IMS CFH Internal expansion RAM size switching register IXS 0CH Oscillation stabilization time select register OSTS 04H Oscillator mode register OS...

Page 274: ...H Baud rate generator control register BRGC 00H Transmit shift register TXS FFH Receive buffer register RXB Serial interface SIO2 Operation mode register 2 CSIM2 00H Shift register 2 SIO2 00H Receive...

Page 275: ...A PD780852 A Internal ROM type Flash memory Mask ROM Internal ROM capacity 40 Kbytes 32 Kbytes 40 Kbytes IC pin None Available VPP pin Available None Electrical specifications See data sheet of each p...

Page 276: ...t sets IMS to CFH Figure 22 1 Memory Size Switching Register IMS Format Address FFF0H After Reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal High S...

Page 277: ...with an 8 bit memory manipulation instruction RESET input sets IXS to 0CH Figure 22 2 Internal Expansion RAM Size Switching Register IXS Format Address FFF4H After Reset 0CH R W Symbol 7 6 5 4 3 2 1 0...

Page 278: ...sed The transmission methods are selected with the VPP pulse numbers shown in Table 22 3 Table 22 3 Transmission Method List Transmission Method Number of Channels Pin Used Note Number of VPP Pulses 3...

Page 279: ...nput data Batch delete Deletes the entire memory contents Batch blank check Checks the deletion status of the entire memory High speed write Performs writing to flash memory according to write start a...

Page 280: ...22 4 22 5 and 22 6 Figure 22 4 Flashpro III Connection Using 3 Wire Serial I O Method SIO3 VPP VDD RESET SCK SO SI GND VPP VDD RESET SCK3 SI3 SO3 VSS Flashpro III PD78F0852 Figure 22 5 Flashpro III C...

Page 281: ...M00 CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the PD780852 Subseries For details of the operation and machine language instruction code refer to the separate document 78K 0...

Page 282: ...A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Formats Identifier Description Format r X R0 A...

Page 283: ...flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register cont...

Page 284: ...e 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A a...

Page 285: ...HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr...

Page 286: ...addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r...

Page 287: ...16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16...

Page 288: ...umulator after Addition Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit sa...

Page 289: ...it CY PSW bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 SET1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr...

Page 290: ...CH SP 1 PCL SP SP SP 2 PCH SP 1 PCL SP RETI 1 6 PSW SP 2 SP SP 3 R R R NMIS 0 PCH SP 1 PCL SP PSW SP 2 SP SP 3 PSW 1 2 SP 1 PSW SP SP 1 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R rpH SP 1...

Page 291: ...set sfr bit BTCLR PC PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC...

Page 292: ...UCTION SET Preliminary User s Manual U14581EJ3V0UM00 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4...

Page 293: ...CH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CM...

Page 294: ...Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR sad...

Page 295: ...addr5 addr16 4 Call branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instructio...

Page 296: ...296 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 297: ...r s Manual U14581EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the PD780852 Subseries Figure A 1 shows the development...

Page 298: ...Real time OS OS Debugging Tools Assembler package C compiler package C library source file Device file Language Processing Software On chip flash memory version In circuit emulator Power unit Emulatio...

Page 299: ...This compiler converts programs written in C language into an object code executable C Compiler Package with a microcontroller This compiler is used in combination with an optional assembler package...

Page 300: ...ersion Note 3P16 HP9000 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Win...

Page 301: ...notebook type as Interface Adapter the IE 78K0 NS host machine It is compatible with the C bus IE 70000 CD IF A These PC card and interface cable are required when using a notebook as the IE 78K0 NS...

Page 302: ...e testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 is used in comb...

Page 303: ...0 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note WindowsNT is not supporte...

Page 304: ...304 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 305: ...ation form in advance and sign the User Agreement Remark and in the part number differ depending on the host machine and OS used S RX78013 Product Outline Upper Limit of Mass Production Quantity 001 E...

Page 306: ...achine and OS used S MX78K0 Product Outline Note 001 Evaluation object Use for trial product XX Object for mass produced product Use for mass produced product S01 Source program Can be purchased only...

Page 307: ...1 MCMPC1 235 Compare control register 2 MCMPC2 235 Compare control register 3 MCMPC3 235 Compare control register 4 MCMPC4 235 Compare register cos side MCMP11 233 Compare register cos side MCMP21 233...

Page 308: ...er IMS 276 O Oscillation stabilization time select register OSTS 264 Oscillator mode register OSCM 93 P Port 0 P0 38 77 Port 1 P1 38 78 Port 2 P2 39 79 Port 3 P3 39 80 Port 4 P4 39 81 Port 5 P5 40 82...

Page 309: ...ration mode register 2 CSIM2 189 Serial operation mode register 3 CSIM3 203 16 bit timer mode control register TMC0 105 16 bit timer register TM0 104 Sound generator amplitude register SGAM 227 Sound...

Page 310: ...egister 2 123 CR3 8 bit compare register 3 123 CRC0 Capture pulse control register 106 CSIM2 Serial operation mode register 2 189 CSIM3 Serial operation mode register 3 203 D DAM1 D A converter mode r...

Page 311: ...P P0 Port 0 38 77 P1 Port 1 38 78 P2 Port 2 39 79 P3 Port 3 39 80 P4 Port 4 39 81 P5 Port 5 40 82 P6 Port 6 40 83 P8 Port 8 41 84 P9 Port 9 41 85 PCC Processor clock control register 92 PFM Power fail...

Page 312: ...gister 191 T TCL1 Timer clock select register 1 115 TCL2 Timer clock select register 2 124 TCL3 Timer clock select register 3 124 TM0 16 bit timer register 104 TM1 8 bit counter 1 114 TM2 8 bit counte...

Page 313: ...on Chapter 2nd edition Changing 1 5 Pin Configuration Top View CHAPTER 1 OUTLINE Changing description of supply voltage in 1 8 Outline of Function Changing 6 4 4 Port mode register 4 PM4 CHAPTER 6 16...

Page 314: ...314 Preliminary User s Manual U14581EJ3V0UM00 MEMO...

Page 315: ...02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 2...

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