NEC mPD780852 Series, Preliminary User'S Manual

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U14581EJ3V0UM00
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
3.1.2 Internal data memory space
The
µ
PD780852 Subseries have the following RAM.
(1) Internal high-speed RAM
The configuration of the internal high-speed RAM is 1,024
×
8 bits at addresses FB00H to FEFFH. The 32-byte
area FEE0H to FEFFH is allocated with four general-purpose register banks composed of eight 8-bit registers.
The internal high-speed RAM can be used as stack memory.
(2) LCD display RAM
An LCD display RAM is allocated to an area of 20
×
4 bits at addresses FA59H to FA6CH. The LCD display
RAM can also be used as a normal RAM.
(3) Internal expansion RAM
An internal expansion RAM is allocated to an area of 512
×
8 bits at addresses F600H to F7FFH.
3.1.3 Special-function register (SFR) area
An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH (see Table
3-3 Special-Function Register List in 3.2.3 Special-function registers (SFRs)).
Caution Do not access addresses where the SFR is not assigned.