NEC mPD780852 Series, Preliminary User'S Manual

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U14581EJ3V0UM00
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE is set to DI, and only non-maskable interrupt request becomes acknowledgeable. Other
interrupt requests are all disabled. When 1, the IE is set to EI and interrupt request acknowledge enable
is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and
a priority specify flag.
The IE is reset (to 0) upon DI instruction execution or interrupt acknowledgement and is set (to 1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (to 1). It is reset (to 0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). It is reset (to 0) in
all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupts specified with a priority specify flag register (PR0L, PR0H, PR1L) (see 19.3 (3)
Priority specify flag registers (PR0L, PR0H, PR1L)) are disabled for acknowledgement. Actual
acknowledgement is controlled with the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction
execution.