UNIVERGE SV8100
Issue 5.0
General Description Manual
5 - 25
6.3
Transmission, Network, and Control Specifications
6.3.1
Transmission
Data Length:
From multiline terminal to CD-8DLCA: 23 bits
From CD-8DLCA to multiline terminal: 23 bits
Data Transmission Rates:
Between CD-8DLCA and multiline terminal: 184K bps (voice and
signaling)
Scanning Time for each multiline terminal: 32ms.
6.3.2
Network
Time Division Multiplexing (TDM) allows transmission of data and
voice simultaneously over one communications medium. The
specifications that the UNIVERGE SV8100 system uses for
switching, clock, data bus, and timeframe are shown below.
TDM Switching: PCM (µ Law)
TDM Clock: 2.048 MHz
TDM Data Bus: 8-bit
TDM Timeframe: 125 µs.
6.3.3
Control
This section indicates the speed or capacity:
Control: Stored program with distributed processing
Central Processor: 32-bit microprocessor
Clock: 266 MHz
Interface Blade: 8- or 16-bit microprocessor
Optional Blades: 16- or 32-bit microprocessor
Multiline Terminal (TDM): 8-bit microprocessor
Multiline Terminal (IP): 32-bit microprocessor
IP Adapter: 32-bit microprocessor
Attendant Console: 4-bit microprocessor
SLT Adapter: 4-bit microprocessor
Summary of Contents for DTL-12BT-1 - DT330 - Plus BCH
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