destinations. If the source signal changes within the setup-and-hold window around the
synchronization clock edge, one of the destinations might go to the new logic level while the
other destination might remain at the old logic level and change when the next synchronization
clock edge occurs, as shown in
on page 30:
Figure 11. Synchronous Routing Uncertainty with Setup-and-Hold Variation
Synchronization CLK
Trigger Output 2
Trigger Ouput 1
Trigger Input
t
setup
t
hold
t
CtoQ
t
CtoQ
Therefore, if your application requires that the trigger arrive at the multiple destinations
simultaneously, you must ensure that the input is stable within the setup and hold window
around the synchronization clock edge. For more information and possible methods to ensure
this requirement is met, go to
ni.com/info
and enter the Info Code
SyncTriggerRouting
.
Possible sources for synchronous routing with the PXIe-6674T include the following sources:
•
Any front panel PFI pin as single ended.
•
Any front panel PFI pin as LVDS.
•
Any PXI star trigger line (PXI_STAR<0..16>)
•
Any PXI trigger line (PXI_TRIG<0..7>)
•
Any PXIe_DSTARC<0..16>
•
Global software trigger
•
The synchronization clock itself.
The synchronization clock for a synchronous route can be any of the following signals:
•
10 MHz PXI_CLK10
•
100 MHz PXIe_CLK100
•
Clock Generation
•
OCXO
•
CLKIN
•
One of two "divided copies" of any of the previously listed five signals. The PXIe-6674T
includes two clock-divider circuits that can divide the synchronization clock signals by
any power of 2 up to 512.
Refer to
on page 22 for an illustration of how the
PXIe-6674T performs synchronous routing operations.
30
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ni.com
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PXIe-6674T User Manual
