Table 3. PXIe-6674T Signals
Signal Name
Direction
Description
PXI_CLK10_IN
Out (to
chassis)
This is a signal that can be used to provide the backplane
with a reference 10 MHZ signal from the system timing
slot. When a 10 MHz signal is connected to
PXI_CLK10_IN, the PXI Express chassis is required to
derive PXI_CLK10 and PXIe_CLK100 from this
reference. Refer to the user manual for your PXI Express
chassis for more information on how it uses
PXI_CLK10_IN.
PXI_CLK10
In (from
chassis)
This signal is the PXI 10 MHz backplane clock. This
signal is the output of the native 100 MHz oscillator in
the chassis divided by ten.
PXIe-CLK100
In (from
chassis)
This signal is the PXI Express 100 MHz backplane clock.
PXIe_CLK100 offers tighter slot to slot timing than
PXI_CLK10.
OCXO Clock
Out
(internal)
This is the output of the 10 MHz OCXO. THe OCXO is
an extremely stable and accurate frequency source.
CLKIN
In (from
front panel)
CLKIN is the signal connected to the SMA input
connector of the same name. CLKIN can be routed
directly to PXI_CLK10_IN, to the 10 MHz PLL, to
PXIe_DSTARA, or to the FPGA.
CLKOUT
Out (to front
panel)
CLKOUT is the signal on the SMA output connector of
the same name. CLKOUT can be sourced from the
OCXO, PXI_CLK10, Clock Generation, or from the
PXIe_DSTARA network.
Clock Generation
Out
(internal)
Clock Generation refers to the clock signal coming from
the onboard clock generation circuitry of the
PXIe-6674T. The clock generation circuitry can generate
a clock from sub-1 Hz to 1 GHz with fine granularity and
is automatically locked in phase to PXIe_CLK100.
PFI<0..5>
In/Out (to/
from front
panel)
The single ended Programmable Function Interface pins
on the PXIe-6674T route timing and triggering signals
between multiple PXI Express chassis. A wide variety of
input and output signals can be routed to or from the PFI
lines.
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PXIe-6674T User Manual
