National Instruments PXIe-6674T, User Manual

Page: 18 / 36

connections that can be made, it is important to understand the underlying hardware
architecture.
Figure 4. on page 18 provides an overview of the PXIe_DSTARA network:
Figure 4. PXIe_DSTARA Network
Source A
Source B
CLKIN
PFI_LVDS<0..2>
Clock Generation
PXIe_DSTARC<0..7>
CLKIN
PFI_LVDS<0..2>
Clock Generation
PXIe_DSTARC<8..16>
PXIe-DSTARA<0..3>
PXIe-DSTARA<4..7>
PXIe-DSTARA<8..11>
PXIe-DSTARA<12..16>
PFI_LVDS
Crosspoint
Switch
Clock Generation
To PFI_LVDS 0
To PFI_LVDS 1
To PFI_LVDS 2
To CLKOUT
Bank 0
Fanout
Bank 1
Fanout
Bank 2
Fanout
Bank 3
Fanout
To drive signals out on the PXIe_DSTARA lines, the PXIe_DSTARA network divides the 17
PXIe_DSTARA lines into four banks, as shown in
Table 5. on page 18:
Table 5. PXIe_DSTARA Divisions
Bank 0 Bank 1 Bank 2 Bank 3
PXIe_DSTARA<0..3> PXIe_DSTARA<4..7> PXIe_DSTARA<8.11> PXIe_DSTARA<12..16>
PFI_LVDS cross point PFI_LVDS cross point PFI_LVDS cross point —
Each one of the Banks can select from either Source A or Source B and all the PXIe_DSTARA
lines that a Bank drives out must share the same source. Banks 0, 1, and 2 send a copy of their
output to the PFI_LVDS cross point switch for routing out the front panel using PFI lines in
LVDS mode. Refer to the
PFI_LVDS<0..2> section for more information.
Note Only clock signals should be routed through the PXIe_DSTARA lines.
PXIe_DSTARA lines may exhibit unexpected behavior when routing conventional
triggers.
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