Figure 9. Synchronous Routing Operation
Trigger Input
Synchronization
Clock
Trigger Output
Setup
Time
t
setup
Hold
Time
t
hold
Clock to Output
Time, t
CtoQ
The PXIe-6674T board supports synchronous routing to either the rising or falling edge of the
synchronization clock. In addition, the polarity of the destination signal can be inverted, which
is useful when handling active-low digital signals. Synchronous routing can be useful for
eliminating skew when sending triggers to several destinations. For example, when sending
triggers using the PXI Trigger lines, the trigger arrives at each slot at a slightly different time.
However, if the trigger is sent and received synchronously using a low-skew synchronization
clock (for example, PXI_CLK10), all receiving devices can act on the trigger at the same time,
as shown in
on page 29:
Figure 10. Synchronous Routing to Multiple Destinations
PXI_CLK10
Trigger@Destination 2
Trigger@Destination 1
Trigger Out@Source
Trigger Synchronously Received
@Destinations 1 and 2
A
B
A: Propagation delay from source to destination 1.
B: Propagation delay from source to destination 2.
Synchronous routing requires the input to be stable at a logic low or logic high state within a
window of time around the clock edge. This window of time around the clock edge is defined
by the setup time (t
setup
) and hold time (t
hold
). If the input signal changes within this window of
time, it is undetermined whether the output of the synchronous route will go to the old or new
logic state. This is important, for example, if a source is being routed synchronously to several
PXIe-6674T User Manual
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© National Instruments
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