1.6 V step—a +3.3 V step split across the 50 Ω resistors at the source and the
destination.
You also can drive a 50 Ω cable with a high-impedance load. The destination sees a single step
to +3.3 V, but the source sees a reflection. This cable configuration is acceptable for low-
frequency signals or short cables.
You can independently select the output signal source for each PFI line from one of the
following sources.
•
Another PFI<0..5>
•
Another PFI pair in LVDS mode.
•
PXI triggers <0..7> (PXI_TRIG<0..7>
•
PXI_STAR<0..16>
•
Global software trigger
•
PFI synchronization clock
•
PXIe_DSTARC
•
Steady logic high or low.
The PXI synchronization clock may be any of the following signals:
•
Clock Generation
•
PXI_CLK10
•
PXIe_CLK100
•
OCXO
•
CLKIN
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
•
Any of the previously listed signals divided by the second frequency divider(2
m
, up to
512)
Refer to
section for more information on the sychronization
clock.
Note
The PFI synchronization clock is the same for all routing operations in which
PFI<0..5> or PFI_LVDS<0..2> is defined as the output, although the divide-down
ratio for this clock (full rate, first divider, second divider) may be chosen on a per-
route basis.
Using Front Panel PFIs for LVDS Triggers
To allow for sending and receiving signals between system timing modules that are too fast for
single ended PFI signaling, two PFI SMA connectors can be combined to send or receive
LVDS signals.
on page 19 shows the relation between the front panel SMA
connectors used for PFI and PFI_LVDS.
When used for trigger routing, the PFI_LVDS signals are routed to and from the FPGA. You
can independently select the output signal source for each PFI_LVDS line from one of the
following sources:
•
Another PFI<0..5>
•
Another PFI pair in LVDS mode.
•
PXI triggers <0..7> (PXI_TRIG<0..7>)
24
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PXIe-6674T User Manual
