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Table 3. PXIe-6674T Signals (Continued)
Signal Name
Direction
Description
PFI_LVDS<0..2>
In/Out (to/
from front
panel)
The LVDS Programmable Function Interface can be used
to route timing and triggering signals between multiple
PXI Express chassis. The use of LVDS logic allows
much faster speeds than can be achieved with the single
ended PFIs. When used as outputs, the LVDS PFIs can be
sourced from the PXIe_DSTARA network, the FPGA, or
the clock generation circuitry. As inputs, the LVDS PFIs
can be routed to the PXIe_DSTARA network and to the
FPGA.
PXI_TRIG<0..7>
In/Out (to/
from
chassis)
The PXI trigger bus consists of eight digital lines shared
among all slots in the PXI Express chassis. The
PXIe-6674T can route a wide variety of signals to and
from these lines.
Note
PXI_TRIG<0..5> are also known as
RTSI<0..5> in some hardware devices and
APIs. However, PXI_TRIG<6..7> are not
identical to RTSI<6..7>.
PXI_STAR<0..16> In/Out (to/
from
chassis)
The PXI star trigger bus connects the system timing slot
to other peripheral slots in a star configuration. The
electrical paths of each star line are closely matched to
minimize intermodule skew. A PXIe-6674T in the system
timing slot can route signals to all available PXI_STAR
lines in the PXI Express chassis.
PXIe_DSTARA
Out (to
chassis)
The PXIe_DSTARA lines connect the system timing
module to each peripheral slot in a PXI Express chassis,
allowing the system timing module to distribute a clock
signal to every slot. PXIe_DSTARA uses differential
LVPECL signaling and is capable of high speed clock
distribution. Refer to
on page
17 for more information.
PXIe-6674T User Manual
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© National Instruments
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