Table 4. Clock Generation Frequency and Resolution
Clock Generation Frequency
Resolution
18.75 MHz to 37.5 MHz
0.355 ΩHz
37.5 MHz to 75 MHz
0.711 ΩHz
75 MHz to 150 MHz
1.42 ΩHz
150 MHz to 300 MHz
2.84 ΩHz
300 MHz to 600 MHz
5.68 ΩHz
600 MHz to 1GHz
11.4 ΩHz
Because the 800 MHz reference of the clock generation circuitry is phase locked to
PXIe_CLK100, its frequency accuracy is inherited from PXIe_CLK100. To give the best
frequency accuracy, the OCXO of the PXIe-6674T can be routed to PXI_CLK10_IN, which
the chassis can then use to lock PXIe_CLK100 and PXI_CLK10. In addition, using the OCXO
will also lower the phase noise of the generated clock frequency.
PXI_CLK10 and PXIe_CLK100
The PXI Express architecture allows a module in the system timing slot to provide a 10 MHz
reference clock to the backplane for use in creating PXI_CLK10 and PXIe_CLK100. This is
done by using the PXI_CLK10_IN pin on the backplane connector.
Most PXI Express backplane architectures employ a PLL to lock a 100 MHz reference
oscillator to the signal coming from the PXI_CLK10_IN pin. This 100 MHz reference is then
used to directly create PXIe_CLK100 and is divided down by ten to create PXI_CLK10. This
architecture has the advantage the PXI_CLK10 and PXIe_CLK100 are always sourced from
the same reference oscillator, and therefore it is impossible to lose PXI_CLK10 or
PXIe_CLK100 by disconnecting the reference provided on PXI_CLK10_IN. For the same
reason, it is also impossible for a runt pulse or glitch to occur on these lines as references are
switched in and out, protecting the integrity of digital circuitry operating on these clocks.
Another feature of this architecture is that the phase noise performance of PXI_CLK10 and
PXIe_CLK100 is fixed beyond the bandwidth of the PLL loop of the backplane, regardless of
the quality of the reference used. This is advantageous if a reference with poor phase noise
performance is used, but it also means that supplying a high end low phase noise reference
will not greatly improve PXI_CLK10 or PXIe_CLK100.
Using PXI_CLK10_IN
The PXIe-6674T provides three options for driving a clock to the backplane using
PXI_CLK10_IN: OCXO, CLKIN, and 10 MHz PLL.
OCXO
The PXIe-6674T features a precision 10 MHz Oven Controlled Crystal Oscillator (OCXO).
The main source of frequency error in reference oscillators is temperature variation. An
OCXO minimizes this error by housing the crystal oscillator circuit inside a sealed oven,
which is maintained at a constant temperature higher than the ambient temperature external to
PXIe-6674T User Manual
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© National Instruments
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