•
PXI_STAR<0..16>
•
Global software trigger
•
PFI synchronization clock
•
PXIe_DSTARC
•
Steady logic high or low.
The PFI synchronization clock is also used for the PFI_LVDS and as such may be one of the
following signals:
•
Clock Generation
•
PXI_CLK10
•
PXIe_CLK100
•
OCXO
•
CLKIN
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
•
Any of the previously listed signals divided by the second frequency divider (2
m
, up to
512)
section for more information on the synchronization
clock.
Note
The PFI synchronization clock is the same for all routing operations in which
PFI<0..5> or PFI_LVDS<0..2> is defined as the output, although the divide-down
ratio for this clock (full rate, first divider, second divider) may be chosen on a per
route basis.
Using the PXI Triggers
The PXI triggers go to all the slots in the chassis. All modules receive the same PXI triggers,
so PXI trigger 0 is the same for the system timing slot as it is for Slot 3, and so on. This feature
makes the PXI triggers convenient in situations where you want, for instance, to start an
acquisition on several devices at the same time because all modules will receive the same
trigger.
The frequency on the PXI triggers should not exceed 5 MHz to preserve signal integrity. The
signals do not reach each slot at precisely the same time. A difference of several nanoseconds
between slots can occur in an eight-slot chassis. However, this delay is not a problem for many
applications.
You can independently select the output signal source for each PXI trigger line from one of the
following sources.
•
PFI<0..5>
•
PFI_LVDS<0..2>
•
Another PXI trigger <0..7> (PXI_TRIG<0..7>)
•
PXI_STAR<0..16>
•
Global software trigger
•
Backplane synchronization clock
•
PXIe_DSTARC
•
Steady logic high or low
PXIe-6674T User Manual
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© National Instruments
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