Note
Because a single integrated circuit is used to make the five outputs in each
bank, tighter skew is achieved within a single Bank than from Bank to Bank.
PFI_LVDS<0..2>
To allow for sending and receiving signals between system timing modules that are too fast for
single ended PFI signaling, two PFI SMA connectors can be combined to send or receive
LVDS signals.
on page 19 shows the relation between the front panel SMA
connectors used for PFI and PFI_LVDS.
Table 6. Combinations of PFI Lines for PFI_LVDS
PFI Line
PFI_LVDS Line
PFI 0
PFI_LVDS 0 Negative
PFI 1
PFI_LVDS 0 Positive
PFI 2
PFI_LVDS 1 Negative
PFI 3
PFI_LVDS 1 Positive
PFI 4
PFI_LVDS 2 Negative
PFI 5
PFI_LVDS 2 Positive
Each of the three PFI_LVDS can be enabled for LVDS operation or used for two single ended
PFIs. When enabled for LVDS operation, the PFI_LVDS pair can be configured as either an
input or an output. PFI_LVDS lines can not be used as an input and output at the same time.
Because of the increased speed capabilities, the PFI_LVDS includes additional routing
capabilities not offered with the single ended PFI. When used as an input, the PFI_LVDS
signal goes to both the FPGA for trigger routing and to the PXIe_DSTARA Network for use in
routing high speed clocks. When used as an output, the PFI_LVDS can be sourced from the
FPGA for trigger usage, or from a 4x4 cross point switch which allows for any of the four
inputs to be connected to any of the four outputs.
on page 19 shows the inputs and
outputs of the cross point switch.
Table 7. PFI_LVDS Inputs and Outputs
Inputs
Outputs
PXIe_DSTARA Network Bank 0
PFI_LVDS 0
PXIe_DSTARA Network Bank 1
PFI_LVDS 1
PXIe_DSTARA Network Bank 2
PFI_LVDS 2
Clock Generation
High Speed CLKOUT
PXIe-6674T User Manual
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© National Instruments
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