Fabric DDR Subsystem
Microsemi ProprietaryUG0446 User Guide Revision 7.0
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DDRC_ADDR_MAP_BANK_CR,
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DDRC_ADDR_MAP_COL_1_CR,
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DDRC_ADDR_MAP_COL_2_CR,
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DDRC_ADDR_MAP_COL_3_CR,
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While configuring the registers, ensure that two DDR memory address bits are not determined by the
same source address bit.
Note:
Some registers map multiple source address bits (REG_DDRC_ADDRMAP_ROW_B0_11)
To arrive at the right address for the DDR controller, the system address or AXI address bits [4:0] are
mapped by the FDDR.
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In Full Bus Width mode, the system address bits [4:0] are used to map the lower column
address bits (C0, C1, C2).
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In Half Bus Width mode, the system address bits [4:0] are used to map the lower column
address bits (C0, C1, C2, C3).
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In quarter bus width mode, the system address bits [4:0] are used to map the lower column
address bits (C0, C1, C2, C3, C4).
The FDDR configurator uses {Row, Bank, Column} address mapping as shown in the following example.
4.6.10.0.1 Example
In this example, the Address map registers are configured to access a 512 MB DDR3 SDRAM memory
(MT41J512M8RA) from the FDDR subsystem as shown in
"Example 2: Connecting 32-Bit DDR3 to
FDDR_PADs with SECDED" section on page 173
. The 512M x 8-bit DDR3 memory module has 3 bank
address lines, 16 rows, and 10 columns.
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The column address bits 3 to 9 are mapped for system address bit[5] to system address bit[11]. To
map the column 3-bit (C3) to address [5], the field is configured to 3, as the base value is 2. Similarly,
the other column address bits are configured:
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DDRC_ADDR_MAP_COL_1_CR = 0x3333
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DDRC_ADDR_MAP_COL_2_CR = 0x3FFF
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DDRC_ADDR_MAP_COL_3_CR = 0x3300
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The bank address bits 0 to 2 are mapped for system address bit[12] to system address bit[14]. To
map the bank bit0 to address [12], the field is configured to A, as the base value is 2. Similarly, the
other bank address bits are configured:
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DDRC_ADDR_MAP_BANK_CR = 0xAAA
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The row address bits 0 to 15 are mapped for system address bit[15] to system address bit[27]. To
map the bank bit0 to address [15], the field is configured to 9, as the base value is 6. Similarly, the
other bank address bits are configured:
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DDRC_ADDR_MAP_ROW_1_CR = 0x9999
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DDRC_ADDR_MAP_ROW_2_CR = 0x9FF
Note:
The FDDR can access the 4 GB address space (0x00000000 - 0xFFFFFFFF). But in this example, 512
MB (0x00000000 - 0x1FFFFFFF) DDR3 SDRAM is connected to the 16 address lines of FDDR. The
memory visible in the other memory space is mirrored of this 512 MB memory.
4.6.10.1 DDR Mode Registers
After reset, the DDR controller initializes the mode registers of DDR memory with the values in the
following registers. The mode registers must be configured according to the specification of the external
DDR memory when the controller is in soft reset.
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DDRC_INIT_MR_CR,
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DDRC_INIT_EMR_CR,
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DDRC_INIT_EMR2_CR,
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DDRC_INIT_EMR3_CR,
The T_MOD and T_MRD bits in DDRC_DRAM_MR_TIMING_PARAM_CR (
configured to the required delay values. T_MOD and T_MRD are delays between loading the mode
registers.
