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4/29/2020

Godson 3A1000 Processor User Manual

RDLVL_OFFSET_DIR

0x0

0x0-0x1

5th data set Read Leveling adjustment direction of midpoint.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

RDLVL_OFFSET_DIR

0x0

0x0-0x1

The adjustment direction of the midpoint during the fourth data set Read Leveling.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

RDLVL_OFFSET_DIR

twenty four 0x0

0x0-0x1

The adjustment direction of the midpoint during the third data set Read Leveling.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

RDLVL_OFFSET_DIR

0x0

0x0-0x1

The adjustment direction of the midpoint during the second data set Read Leveling.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

RDLVL_OFFSET_DIR

0x0

0x0-0x1

The adjustment direction of the midpoint during the first data set Read Leveling.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

RDLVL_OFFSET_DIR

0x0

0x0-0x1

The adjustment direction of the midpoint during the 0th data set Read Leveling.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

CONF_CTL_116 [63: 0] Offset: 0x740 DDR2 667: 0x0100000000000000

AXI1_PORT_ORDERI 57:56

0x0

0x0-0x3 Whether internal port 1 can be executed out of order, invalid for Godson No. 3

Page 71

Godson 3A1000 Processor User Manual Part 1

AXI0_PORT_ORDERI

49:48

0x0

0x0-0x3 Whether internal port 0 can be executed out of order

WRLVL_REQ

0x0

0x0-0x1 User request to start Write Leveling training function. (Write only)

WRLVL_INTERVAL_C

T_EN

0x0

0x0-0x1 Enable Write Leveling time interval function

WEIGHTED_ROUND_

ROBIN_WEIGHT_SH

ARING

twenty four 0x0

0x0-0x1 Per-port pair shared arbitration for WRR

WEIGHTED_ROUND_

ROBIN_LATENCY_

CONTROL

0x0

0x0-0x1 Free-running or limited WRR latency counters.

RDLVL_REQ

0x0

0x0-0x1 User request to start the Read Leveling training function. (Write only)

RDLVL_OFFSET_DIR

0x0

0x0-0x1

The 8th data set Read Leveling adjustment direction of the midpoint.

When 0, the midpoint is calculated by subtracting rdlvl_offset_delay, which is

1 is added.

CONF_CTL_117 [63: 0] Offset: 0x750 DDR2 667: 0x0100000101020101

WRLVL_CS

57:56

0x0

0x0-0x3 indicates the chip select signal of the current Write Leveling operation

SW_LEVELING_MOD

49:48

0x0

0x0-0x3 Define the mode of software leveling operation

RDLVL_CS

41:40

0x0

0x0-0x3 indicates the chip select signal of the current Read Leveling operation

AXI2_W_PRIORITY

33:32

0x0

0x0-0x3 The write priority of internal port 2 is invalid for Godson No. 3

AXI2_R_PRIORITY

25:24

0x0

0x0-0x3 The read priority of internal port 2 is invalid for Godson No. 3

AXI2_PORT_ORDERI

17:16

0x0

0x0-0x3 Whether internal port 2 can be executed out of order, invalid for Godson 3

Summary of Contents for Godson 3A1000

Page 1: ...sor User Manual 1 Page 1 Godson 3A1000 Processor User Manual volume One Multi core processor architecture register description and system software programming guide V1 15 2015 Nian 09 Yue Loongson Zho...

Page 2: ...al Protection Technology Demonstration Park Haidian District Beijing Building No 2 Loongson Industrial Park Zhongguancun Environmental Protection Park Haidian District Beijing Telephone Tel 010 625466...

Page 3: ...n of PCI_CONFIG to configuration pins 3 2010 06 25 V1 2 Add the second part of the manual including the configuration and use of interrupts serial port configuration and Use EJTAG debugging instructio...

Page 4: ...egister 12 2012 08 23 V1 11 revised DDR parameter definition Add the definition of HT register supported by LS3A1000E 13 2012 10 30 V1 12 Added matrix handling register supported by LS3A1000E 14 2014...

Page 5: ...tem 8 2 5 Address Routing Distribution and Configuration 10 2 6 Chip Configuration and Sampling Register 16 3 GS464 processor core 19 4 Secondary Cache twenty one 5 Matrix processing accelerator twent...

Page 6: ...onfiguration register 95 9 5 14 HyperTransport bus configuration space access method 96 9 6 HyperTransport multiprocessor support 96 10 Low speed IO controller configuration 99 10 1 PCI PCI X controll...

Page 7: ...w of primary crossbar 134 14 3 Timing of configuring the address window of the first level crossbar 136 14 4 Address window of secondary crossbar switch 136 III Page 9 Godson 3A1000 processor user man...

Page 8: ...2 SDRAM read operation protocol 32 Figure 8 3 DDR2 SDRAM write operation protocol 32 Figure 9 1 HT protocol configuration access in Loongson No 3 96 Figure 9 2 Four piece Loongson No 3 interconnection...

Page 9: ...rface description twenty three Table 5 2 Matrix processing register address description twenty three Table 5 3 Explanation of the trans_ctrl register twenty four Table 5 4 Explanations of the trans_st...

Page 10: ...re visible registers in this module 82 Table 10 1 PCIX Controller Configuration Header 99 Table 10 2 PCI Control Register 100 Table 10 3 PCI PCIX bus request and response line allocation 103 Table 10...

Page 11: ...The above three series will be developed in parallel Loongson No 3 multi core series processor is based on a scalable multi core interconnect architecture design integrating multiple high end on a si...

Page 12: ...ur directions of east south west and north through four pairs of Master Slave Other nodes or IO nodes EM ES SM SS WM WS NM NS in the figure The X2 crossbar is connected to four secondary caches throug...

Page 13: ...Memory Controller Config Register Test Controlle r EJTAG TAP Controlle r Test Interface JTAG Interface Inter chip Link SouthBridge I O Link DDR2 3 SDRAM Low end I O Interface Inter chip Link SouthBrid...

Page 14: ...ontents of the Godson 3A screening test are as follows Filter items Methods and conditions Summary Claim 1 Visual inspection The logo is clear no contamination no solder ball oxidation and the chip is...

Page 15: ...reference voltage CLKSEL 14 1 b1 means HT PLL uses differential clock input 1 b0 means HT PLL uses normal clock input CLKSEL 13 12 2 b00 means the PHY clock is 1 6GHZ 1 2 b01 means the PHY clock is 3...

Page 16: ...e at the node level of the system The system physical address distribution of Loongson No 3 series processors adopts a globally accessible hierarchical addressing design to System development is compa...

Page 17: ...0_0000 south 5 0xa00_0000_0000 0xc00_0000_0000 oo 6 0xc00_0000_0000 0xe00_0000_0000 north 7 0xe00_0000_0000 0x1000_0000_0000 For example the base address of the east port device of node 0 is 0x0800_00...

Page 18: ...f0_2100 CORE1_WIN0_BASE 0x3ff0_2008 CORE0_WIN1_BASE 0x3ff0_2108 CORE1_WIN1_BASE 0x3ff0_2010 CORE0_WIN2_BASE 0x3ff0_2110 CORE1_WIN2_BASE 0x3ff0_2018 CORE0_WIN3_BASE 0x3ff0_2118 CORE1_WIN3_BASE 0x3ff0_2...

Page 19: ...0_2398 CORE3_WIN3_MMAP 0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff0_23a0 CORE3_WIN4_MMAP 0x3ff0_22a8 CORE2_WIN5_MMAP 0x3ff0_23a8 CORE3_WIN5_MMAP 0x3ff0_22b0 CORE2_WIN6_MMAP 0x3ff0_23b0 CORE3_WIN6_MMAP 0x3ff0_22...

Page 20: ...IN0_MMAP 0x3ff0_2688 WEST_WIN1_MMAP 0x3ff0_2788 NORTH_WIN1_MMAP 0x3ff0_2690 WEST_WIN2_MMAP 0x3ff0_2790 NORTH_WIN2_MMAP 0x3ff0_2698 WEST_WIN3_MMAP 0x3ff0_2798 NORTH_WIN3_MMAP 0x3ff0_26a0 WEST_WIN4_MMAP...

Page 21: ...f0 0000 CPU_WIN0_BASE CPU window 0 base address 0x0 3ff0 0008 CPU_WIN1_BASE CPU window 1 base address 0x1000_0000 3ff0 0010 CPU_WIN2_BASE CPU window 2 base address 0x0 3ff0 0018 CPU_WIN3_BASE CPU wind...

Page 22: ...ase address of PCI window 2 0 3ff0 0198 PCI_WIN3_MMAP PCI window 3 new base address 0 3ff0 01a0 PCI_WIN4_MMAP PCI window 4 new base address 0x0 3ff0 01a8 PCI_WIN5_MMAP PCI window 5 new base address 0x...

Page 23: ...e 1 Disabled 0 Do not disable 9 DDR_buffer_cpu RW 1 b0 Whether to open DDR read access buffer 1 open 0 disabled 12 Core0_en RW 1 b1 Whether to enable processor core 0 1 open 0 disabled 13 Core1_en RW...

Page 24: ...ield name access Reset value description 15 0 Pad2v5_ctrl RW 16 h780 2v5pad control 31 16 Pad3v3_ctrl RW 16 h780 3v3pad control 17 Page 30 Godson 3A1000 Processor User Manual Part 1 47 32 Sys_clksel R...

Page 25: ...nt component supports full pipe 64 bit dual 32 bit floating point multiply add operations The memory access component supports 128 bit memory access and the virtual address and physical address are 48...

Page 26: ...DTLB ROQ BRQ Integer Register File AGU Write back Bus Commit Bus Map Bus missq Refill Bus imemread dmemwrite D ecoder R egister M apper P C PC 16 dmemread duncache ucqueue wtbkqueue AXI Interface EJT...

Page 27: ...le reading The TAG directory and data of all channels are output and the data and directory are selected according to the TAG Replace request refill request and write back Request to operate only TAG...

Page 28: ...f data so that these data can be written in Cache rows in the transposed matrix Input so a buffer area with a size of 32 lines is set in the module to achieve horizontal writing reading from the sourc...

Page 29: ...The length of transpose module 1 0x3ff00728 Width of transpose module 1 0x3ff00730 Trans_ctrl of transpose module 1 0x3ff00738 Trans_status of transpose module 1 Table 5 3 Explanation of the trans_ct...

Page 30: ...7 Godson 3A1000 Processor User Manual Part 1 Table 5 4 Explanations of the trans_status registers Field Explanation 0 Source matrix read 1 The target matrix is written 25 Page 38 Godson 3A1000 Process...

Page 31: ...000 R IPI_Status register of processor core 0 Core0_IPI_Enalbe 0x3ff01004 RW IPI_Enalbe register of processor core 0 Core0_IPI_Set 0x3ff01008 W IPI_Set register of processor core 0 Core0 _IPI_Clear 0x...

Page 32: ...osed of a single Loongson 3A1000 chip Memory list When using multiple Loongson 3A1000 interconnects to form a multi node CC NUMA system the node pairs in each chip Should be a system global node numbe...

Page 33: ...rix_int1 10 RO 1 R 0 RW 0 RW 0 Lpc 12 11 RW 0 Keep Keep Keep Mc0 1 13 RW 0 R 0 RW 0 RW 0 Barrier 14 RW 0 R 0 RW 0 RW 0 Keep 15 RW 0 R 0 RW 0 RW 0 Pci_perr 23 16 RW 0 R 0 RW 0 RW 0 HT0 int0 7 31 24 RW...

Page 34: ...nt3 Entry4 0x3ff01405 Pci_int0 Entry20 0x3ff01414 HT0 int4 Entry5 0x3ff01406 Pci_int1 Entry21 0x3ff01415 HT0 int5 Entry6 0x3ff01407 Pci_int2 Entry22 0x3ff01416 HT0 int6 Entry7 0x3ff01408 Pci_int3 Entr...

Page 35: ...space as an example follow the configuration below Chip select 4 Bank number 8 Number of row addresses 12 Number of column addresses 12 Figure 8 1 Conversion of DDR2 SDRAM row and column addresses an...

Page 36: ...e cleared to their initial values 2 The system is reset 3 Send a 64 bit write command to the configuration register address to configure all 180 configuration registers If you write CTRL_03 the parame...

Page 37: ...0 0x1 When the write operation detects an unrecoverable error is it forbidden to Memory verification code is set to error DQS_N_EN 16 16 0x0 0x0 0x1 Set whether the DQS signal is single ended or diffe...

Page 38: ...SH _EXIT 0 0 0x0 0x0 0x1 Use self refresh command instead of normal memory initialization Command to exit power down mode CONF_CTL_04 63 0 Offset 0x40 DDR2 667 0x0102010100010101 RTT_0 57 56 0x0 0x0 0...

Page 39: ...DT The signal is valid Note When WRLAT CASLAT_LIN 2 it will not Add an extra delay between CS reading and writing TWTR 42 40 0x0 0x0 0x7 Define the clock period required to switch from write command t...

Page 40: ...istance is valid the specific configuration should refer to the corresponding memory chip The requirements for ODT configuration in the manual The four digits of the parameter Do not correspond to CS0...

Page 41: ...used when there are 8 logical banks CONF_CTL_12 63 0 Offset 0xc0 DDR2 667 0x00002c0511000000 TRFC 47 40 0x0 0x0 0xff Define the number of clock cycles required for the refresh operation of the memory...

Page 42: ...ess information when a 1bit ECC error occurs read only TINIT 23 0 0x0000 0x0 0xfffff Define the number of clock cycles required for memory module initialization Configure according to specific memory...

Page 43: ...1 disable output clock signal number ODT_ALT_EN 8 8 0x0 0x0 0x1 Whether to support the ODT signal when CAS 3 Note For Godson No 3 invalid DRIVE_DQ_DQS 0 0 0x0 0x0 0x1 Set whether to drive the data bu...

Page 44: ...tter number 24 Control the enable signal of internal DLL when it is 0 DLL works 23 16 Between control write data DQ and DQS Phase relationship each value is expressed as 1 precision 360 In Godson 3 th...

Page 45: ...23 16 Control the phase between write data DQ and DQS Relationship each value is expressed as 1 precision 360 In Godson 3 In the number this value is generally 1 4 which is 8 h20 7 0 Control the accu...

Page 46: ...ata group in test mode read only CONF_CTL_42 63 0 Offset 0x2a0 DDR2 667 0x0x0000000000000000 DLL_OBS_REG_0_4 33 32 0x0 0x0 0x3 DLL output of the 4th data group in test mode read only DLL_OBS_REG_0_3 1...

Page 47: ...ack pin active low 14 Output enable signal corresponding to the data strobe pin active low 13 Output enable signal corresponding to the data shield pin active low 12 Output enable signal corresponding...

Page 48: ...riting DQS 6 4 Start time when writing data is valid 2 0 End time when writing data is valid PHY_CTRL_REG_0_1 31 0 0x00000 0x0 0xffffffff Delay control of the first data group 28 Whether to use deburr...

Page 49: ...ve end time for writing DQS 6 4 Start time when writing data is valid 2 0 End time when writing data is valid PHY_CTRL_REG_0_3 31 0 0x0000 0x0 0xffffffff Data group 3 delay control 28 Whether to use d...

Page 50: ...eamble DQS 11 8 The effective end time for writing DQS 6 4 Start time when writing data is valid 2 0 End time when writing data is valid PHY_CTRL_REG_0_5 31 0 0x000000 00 0x0 0xffffffff Data group 5 d...

Page 51: ...ould be opened one cycle earlier than DDR2 to provide particle requirements Preamble DQS 11 8 The effective end time for writing DQS 6 4 Start time when writing data is valid 2 0 End time when writing...

Page 52: ...nly 1 bit is valid for controlling Opening timing of the DQS sampling window PHY_CTRL_REG_1_0 31 0 0x00000 0x0 0xffffffff Terminal resistance control of PAD in data group 0 initiate read operation Wil...

Page 53: ...27 24 Timing control of terminal resistance off 23 Effective level control of termination resistance Is 1 22 Enable signal of the terminating resistor when it is 1 the dynamic square is used The contr...

Page 54: ...16 Test signal normally 0 14 12 Test signal normally 0 11 8 read sampling delay 1 of which only 1 bit is valid used for Control when DQS sampling window is closed 7 0 read sampling delay 0 of which o...

Page 55: ...mpling window CONF_CTL_54 63 0 Offset 0x360 DDR2 667 0x0800c00507c00000 PHY_CTRL_REG_2 63 32 0x00000 0x0 0xffffffff Read and write data delay control 27 Select the read data buffer type the default is...

Page 56: ...t 0x3a0 DDR2 667 0x0000000000000000 PHY_OBS_REG_0_7 63 32 0x00000 0x0 0xffffffff 7th data set test observation signal read only PHY_OBS_REG_0_6 31 0 0x00000 0x0 0xffffffff Observation signal for the 6...

Page 57: ...0 0x0 0x3 Whether internal port 1 can be executed out of order invalid for Godson No 3 58 Page 71 Godson 3A1000 Processor User Manual Part 1 NG AXI0_PORT_ORDERI NG 49 48 0x0 0x0 0x3 Whether internal p...

Page 58: ...s for Godson 3 is invalid AXI2_PRIORITY1_RE LATIVE_PRIORITY 51 48 0x0 0x0 0xf The relative priority of the internal port 2 priority 1 command for Godson 3 is invalid AXI2_PRIORITY0_RE LATIVE_PRIORITY...

Page 59: ...controller is idle The control bit is the same as LOWERPOWER_CONTROL ZQCS_CHIP 27 24 0x0 0x0 0xf defines the valid chip selection for the next ZQ WRR_PARAM_VALUE _ERR 19 16 0x0 0x0 0xf Errors warnings...

Page 60: ...lue of sampling training RDLVL_GATE_CLK_A DJUST_5 15 8 0x00 0x0 0xff In the fifth data set read the start value of the sample training RDLVL_GATE_CLK_A DJUST_4 7 0 0x00 0x0 0xff In the fourth data set...

Page 61: ...000000000000 63 Page 76 Godson 3A1000 Processor User Manual Part 1 OBSOLETE CONF_CTL_138 63 0 Offset 0x8a0 DDR2 667 0x00000000001c001c LOWPOWER_INTER NAL_CNT 63 48 0x0000 0x0 0xffff Counts idle cycles...

Page 62: ...ffff read back mask during sampling training RDLVL_GATE_RESP_ MASK 31 0 31 0 0x0000000 0 0x0 0xffffffff read back mask during sampling training CONF_CTL_146 63 0 Offset 0x920 DDR2 667 0x00000000000000...

Page 63: ...in multiple ECCs is found 2 One bit error in ECC is found at a time 1 Multiple accesses exceeding the physical space of memory are found 0 An access is found that exceeds the physical space of memory...

Page 64: ...fore the read operation To prevent concurrent auto precharge operations CKE_STATUS 48 0x0 0x0 0x1 indicates CKE_STATUS read only INT_ACK 41 24 0x00 0x0 0x3ffff Interrupt clear write only 17 User initi...

Page 65: ...erent chip select Number of cycles TBST_INT_INTERVAL 42 40 0x0 0x0 0x7 DRAM burst interrupt interval period 68 Page 81 Godson 3A1000 Processor User Manual Part 1 R2W_SAMECS_DLY 34 32 0x0 0x0 0x7 When...

Page 66: ...520a52 MR1_DATA_0 62 48 0x0 0x0 0x7fff corresponds to the configuration value of the mode register 1 of chip select 0 MR0_DATA_3 46 32 0x0 0x0 0x7fff corresponds to the configuration value of mode reg...

Page 67: ...from the first 1 to the Read Leveling 0 number of delay units RDLVL_BEGIN_DELA Y_4 15 0 0x0 0x0 0xffff In the 4th data group from the first 1 to the Read Leveling 0 number of delay units CONF_CTL_163...

Page 68: ...group from the first 0 to the Read Leveling 1 number of delay units RDLVL_END_DELAY_ 6 15 0 0x0 0x0 0xffff In the 6th data group from the first 0 to the Read Leveling 1 number of delay units CONF_CTL_...

Page 69: ...ed it is equal to of rdlvl_begin_delay_1 and rdlvl_end_delay_1 Interval otherwise equal to rdlvl_delay_1 read only CONF_CTL_172 63 0 Offset 0xac0 DDR2 667 0x0000000000000000 RDLVL_MIDPOINT_D 63 48 0x0...

Page 70: ...0 0xffff In the 5th data group control the number of write DQS via DLL delay WRLVL_DELAY_4 47 32 0x0 0x0 0xffff In the 4th data group control the number of write DQS via DLL delay WRLVL_DELAY_3 31 16...

Page 71: ...lize see section x 1 for details The main characteristics of Godson 3 HyperTransport controller are as follows Support 200 400 800Mhz Support 8 16 bit width Each HT controller HT0 HT1 can be configure...

Page 72: ...t in control When the receiving window of the controller hits it will be sent back to the bus as a P2P request such as If this register is 1 there is no hit it will respond as an error request 0 Set H...

Page 73: ...mode Extension consistency 000000 NOP Empty package or flow control 000001 NPC FLUSH No operation x01xxx NPC or PC Write bit 5 0 Nonposted 1 Posted bit 2 0 Byte 1 Doubleword bit 1 Don t Care bit 0 Don...

Page 74: ...h is to The PIC controller issues a clear interrupt After that the process of the next interrupt is started 9 4 HyperTransport address window 9 4 1 HyperTransport space In the Godson 3 processor the d...

Page 75: ...will enter the processor Row write access complete response Prefetch window See window configuration 9 5 9 2 Internal bus Determine whether to receive Department s Cache access Fetch access When the p...

Page 76: ...0x98 HT Bus Interrupt Vector Register 223 192 0x9C HT Bus Interrupt Vector Register 255 224 0xA0 Interrupt enable register HT bus interrupt enable register 31 0 0xA4 HT bus interrupt enable register 6...

Page 77: ...bus twenty three Reserved 1 0x0 Keep 22 18 Unit ID 5 0x0 In R W HOST mode can be used to record the number of IDs used In SLAVE mode record your own Unit ID 17 Double Ended 1 0x0 R No dual HOST mode 8...

Page 78: ...dson 3A1000 Processor User Manual Part 1 Offset 0x48 Reset value 0x80250023 Name Revision ID Link Freq Link Error Link Freq Cap Bit field Bit field name Bit width reset value Visit description 31 16 L...

Page 79: ...qid 1 0x0 Does R W don t care about HT order relationship 20 Not Axi2Seqid 1 0x1 R Whether to convert the commands on the Axi bus to different SeqIDs If not converted all read and write commands will...

Page 80: ...0x8 R W receive buffer npc command buffer initialization information 3 0 rx_buffer_pc_cmd 4 0x8 R W receive buffer pc command buffer initialization information 9 5 7 Receive Address Window Configurat...

Page 81: ...ess Bit field Bit field name Bit width reset value Visit description 31 ht_rx_image2_en 1 0x0 R W HT bus receives address window 2 enable signal 30 ht_rx_image2_ trans_en 1 0x0 R W HT bus receives add...

Page 82: ...89 Page 102 Godson 3A1000 Processor User Manual Part 1 Offset 0x80 Reset value 0x00000000 Name HT Bus Interrupt Vector Register 31 0 Bit field Bit field name Bit width reset value Visit description 3...

Page 83: ...t vector registers Set 1 to enable the corresponding interrupt set 0 to Interrupt masking Offset 0xa0 Reset value 0x00000000 Name HT Bus Interrupt Enable Register 31 0 Bit field Bit field name Bit wid...

Page 84: ...ield name Bit width reset value Visit description 31 0 Interrupt_mask 255 224 32 0x0 R W HT bus interrupt enable register 255 224 Corresponding to interrupt line 3 HT HI Corresponding to interrupt lin...

Page 85: ...00000000 Name HT bus POST address window 0 base address internal access Bit field Bit field name Bit width reset value Visit description 31 16 ht_post0_base 39 24 16 0x0 R W HT bus POST address window...

Page 86: ...bus can pre fetch the address window 1 the translated address 39 24 Offset 0xec Reset value 0x00000000 Name HT bus prefetchable address window 1 base address internal access Bit field Bit field name B...

Page 87: ...1 16 ht_uncache1_ base 39 24 16 0x0 R W HT bus uncache address window 1 address base address 39 24 15 0 ht_uncache1_ mask 39 24 16 0x0 R W HT bus uncache address window 1 address masked 39 24 9 5 14 H...

Page 88: ...ection can be used between the two processors Two chip numbers Don t be 00 and 01 From the routing algorithm we can know that when two chips access each other they are interconnected with 8 bit HT bus...

Page 89: ...ded by the address Send to the appropriate device 10 1 PCI PCI X controller The PCI PCI X controller of Loongson 3 can be used as the main bridge to control the entire system or it can be used as an o...

Page 90: ...he size enable and other details of the The three corresponding registers PCI_Hit0_Sel PCI_Hit1_Sel PCI_Hit2_Sel control please refer to Table 2 for specific bit fields Table 10 2 PCI Control Register...

Page 91: ...cess timeout 1 not allowed REG_44 31 0 Reserved REG_48 31 0 tar_pending_seq Read and write 0 target unprocessed request number bit vector The corresponding bit can be cleared by writing 1 REG_4C 31 30...

Page 92: ...d and write 0 master retry cancellation write 1 to clear 16 mas_trdy_timeout Read and write 0 master TRDY timeout count 15 8 mas_retry_value Read and write 00h master retries 0 unlimited retry 1 255 1...

Page 93: ...Support LPC access timeout counter Supports Memory Read and Memory write access types Support Firmware Memory Read Firmware Memory Write access type single byte Supports I O read and I O write access...

Page 94: ...The UART controller has the following features Full duplex asynchronous data receiving sending Programmable data format 16 bit programmable clock counter Support receiving timeout detection Multi int...

Page 95: ...bit Interrupt control function table Bit 3 Bit 2 Bit 1 Priority Type of interrupt Interrupt source Interrupt reset control 0 1 1 1st Receiving line state Parity overflow or frame error or Interrupt Re...

Page 96: ...ster 6 bcb 1 RW Interrupt control bit 1 At this time the output of the serial port is set to 0 interrupted state 0 normal operation 5 spb 1 RW Specify parity 0 no parity bit specified 1 transmission a...

Page 97: ...onnections are as follows DTR DSR RTS CTS Out1 RI Out2 DCD 3 OUT2 1 W Connect to DCD input in loopback mode 2 OUT1 1 W Connect to RI input in loopback mode 1 RTSC 1 W RTS signal control bit 0 DTRC 1 W...

Page 98: ...LSR 4 1 and LSR 7 are cleared and LSR 6 5 when writing data to the transmit FIFO Cleared LSR 0 judges the receive FIFO 10 3 8 MODEM status register MSR Chinese name Modem Status Register Register bit...

Page 99: ...ical address of the SPI controller module register is 0x1FE001F0 10 4 1 Control Register SPCR Chinese name Control Register Register bit width 7 0 Offset 0x00 Reset value 0x10 Bit field Bit field name...

Page 100: ...ld name Bit width access description 7 0 Tx FIFO 8 W Data transfer register 10 4 4 External register SPER Chinese name external register Register bit width 7 0 Offset 0x03 Reset value 0x00 Bit field B...

Page 101: ...GPIO_Data GPIO data 20 GPIO_EN GPIO direction twenty four Keep 28 Keep 2C Keep 30 Keep 34 Keep 38 Keep 3C Keep 40 Mem_Win_Base_L Prefetch the lower 32 bits of the base address of the window 44 Mem_Win...

Page 102: ...127 Godson 3A1000 Processor User Manual Part 1 5 0 pcix_rgate Read and write 6 h18 Threshold for sending data to DDR2 in PCIX mode 6 pcix_ro_en Read write 0 Does the PCIX bridge allow write over read...

Page 103: ...e 1 b0 Whether to open DDR read access buffer 12 Core0_en Read and write 1 b1 Whether to enable processor core 0 13 Core1_en Read and write 1 b1 Whether to enable processor core 1 14 Core2_en Read and...

Page 104: ...ed Near temperature accuracy is 6 degrees Celsius 116 Page 129 Godson 3A1000 Processor User Manual Part 1 103 Thsens0_overflow Read only Temperature sensor 0 temperature overflow over 128 degrees 110...

Page 105: ...cessor User Manual Part 2 11 Interrupt configuration and use 11 1 Interrupted process The process of Loongson 3A1000 handling interrupts from the external interrupt request to the kernel s handling of...

Page 106: ...enable trigger and route the interrupt pin of the target processor core 119 Page 132 Godson 3A1000 Processor User Manual Part 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 twenty three 16 31 twenty four IP0...

Page 107: ...name Address offset description name Address offset description Entry0 0x1400 Sys_int0 Entry16 0x1410 HT0 int0 Entry1 0x1401 Sys_int1 Entry17 0x1411 HT0 int1 Entry2 0x1402 Sys_int2 Entry18 0x1412 HT0...

Page 108: ...has three registers Intenset Intenclr and Inten Intenset Set the interrupt enable and the interrupt corresponding to the write 1 bit in the Intenset register is enabled Intenclr clear interrupt enable...

Page 109: ...t In the trap_init function the abnormal general entry address is set Set to 0x80000180 this address holds a function pointer as expect_vec3_generic see the kernel arch mips kernel genex S The expect_...

Page 110: ...T1 The base address of the serial register of UART0 is 0xbfe001e0 the base address of the serial register of UART1 is 0xbfe001e8 The baud rate is 115200 there is another type of LPC UART whose base ad...

Page 111: ...re are three main files for configuring the serial port in the Linux kernel include asm serial h arch mips kernel 8250 platform c arch mips lemote ev3a dbg_io c These three configuration files involve...

Page 112: ...on serial interrupts in irq c Points are as follows 126 Page 139 Godson 3A1000 Processor User Manual Part 2 else if pending CAUSEF_IP2 For LPC ifdef CONFIG_CPU_UART do_IRQ 58 else irq volatile unsign...

Page 113: ...oard into debug mode and turn to execute the debug service Cheng There are two entrances to the debug service which are located at 0xbfc00480 in the BIOS and at the EJTAG debug memory interface 0xff20...

Page 114: ...rite size 3 address 000000000000000f value 0000000000000000 t1 pracc write size 3 address 0000000000000017 value 0000000000000000 t2 129 Page 142 Godson 3A1000 Processor User Manual Part 2 pracc write...

Page 115: ...00000000000 pracc write size 3 address 0000000000000107 value fff3ffffbfc00480 pracc write size 3 address 0000000000000107 value 0000000000000003 pracc write size 3 address 0000000000000107 value 0000...

Page 116: ...lb lh lw ld beqzl t2 1f lb t5 0x0 t1 addiu t2 t2 1 beqzl t2 1f lh t5 0x0 t1 addiu t2 t2 1 beqzl t2 1f lw t5 0x0 t1 addiu t2 t2 1 ld t5 0x0 t1 1 sd t5 0x208 t0 read the return value read_end write ld...

Page 117: ...to be modified in the common MIPS debugging platform And increase the corresponding debugging service program This feature has not been implemented 133 Page 146 Godson 3A1000 Processor User Manual Pa...

Page 118: ...th the address before mapping that is the primary port address The address and the configuration on the secondary crossbar switch are not subject to this restriction 14 2 Address window of primary cro...

Page 119: ...to secondary cache 1 0x800 Route to secondary cache 2 0xc00 Route to secondary cache 3 0x0C00_0000_0000 0x0DFF_FFFF_FFFF HyperTransport 0 0x0E00_0000_0000 0x0FFF_FFFF_FFFF HyperTransport 1 14 3 Timin...

Page 120: ...on device 0 Work stored some valid data After configuring the address window set the system address to 0x0000_2000_0000 0x0000_2FFFF_FFFF is mapped to 0x0000_0000_0000 of memory controller 0 0x0000_0F...

Page 121: ...7 0x0000_0000_0000_0C00 0x0000_0000_0000_0C00 0x0000_0000_0000_0CF3 From this window we can see that all addresses that did not hit in windows 0 3 will be hit in these 4 windows and according to scid...

Page 122: ...register offset of the external device to The following rules allow direct read and write access to the address Type 0 Type 1 14 6 2 Address window for external device to DMA access to processor chip...

Page 123: ...00F7 Window 2 0x0000_0000_1E00_0000 0xFFFF_FFFF_FF00_0000 0x0000_0E00_0000_00F7 Window 3 Window 4 0x0000_0C00_0000_0000 0xFFFF_FC00_0000_0000 0x0000_0C00_0000_00F7 Window 5 Window 6 0x0000_1000_0000_0...

Page 124: ...ue to the way Linux handles the HT MEM space it still needs to convert the HT MEM space to simplify the 32 Access to peripherals addressed by bit addresses The remaining windows are used to route all...

Page 125: ...of the low speed device space so that it can be guaranteed to fall in this window The visit of the mouth is the visit that the procedure needs to make Window 1 opens all types of access to the BOOT s...

Page 126: ...cache access and instruction fetch Normal visits including visits guess visits can make normal visits to this space Window 2 opens the lower 256MB space on memory controller 0 allowing all types of ac...

Page 127: ...e access delay and average access bandwidth of the system but it is subject to the configuration of the crossbar To limit the number of windows certain rules must be adopted to design a certain method...

Page 128: ...aved we configure the two level crossbar as follows On the memory address space Explanation window Used to enable access to the BIOS space 0 BASE 0x00000000_1FC00000 MASK 0xFFFFFFFF_FFF00000 MMAP 0x00...

Page 129: ...00 MASK 0xFFFFFFFF_E0000400 MMAP 0x00000000_000000F1 6 BASE 0x00000000_60000000 MASK 0xFFFFFFFF_E0000400 MMAP 0x00000000_000004F0 7 BASE 0x00000000_60000400 MASK 0xFFFFFFFF_E0000400 MMAP 0x00000000_00...

Page 130: ...00_0000_8000_0000 0x0000_0000_8FFF_FFFF Address 1 256MB 2GB System space 0x0000_0000_9000_0000 0x0000_0000_FFFF_FFFF DMA space 0x0000_0000_9000_0000 0x0000_0000_FFFF_FFFF When using the HyperTransport...

Page 131: ...ocessing image display process For the case of using independent video memory since the video memory is inside the graphics card the process becomes The card can directly write the content to the vide...

Page 132: ...lly 0x10000000 and the corresponding memory address is 0x78000000 this is also achieved through TLB mapping The code for TLB mapping is as follows 151 Page 164 Godson 3A1000 Processor User Manual Part...

Page 133: ...e video memory In this way it actually uses the upper part of the memory This is the structure of ati_nb_cfg in rs690_struct c Set in the body set system_memory_tom_lo to 0x1000M which is 0x100000000...

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