4/29/2020
Godson 3A1000 Processor User Manual
85
Reset value: 0x00000000
Name: IntrInfo [63:32]
Bit field
Bit field name
Bit width reset value Visit description
31: 0
IntrInfo [63:32]
32
0x0
R
Keep
9.5.11
POST address window configuration register
The address window hit formula in this controller is as follows:
hit = (BASE & MASK) == (ADDR & MASK)
It is worth mentioning that when configuring the address window register, the high bit of MASK should be all 1s and the low bit should be all 0s. 0 in MASK
The actual number of bits indicates the size of the address window.
The address in this window is the address received on the AXI bus. All write accesses that fall in this window will immediately be on the AXI B channel
Return and send to the HT bus in the format of POST WRITE command. Instead of writing requests in this window, NONPOST
WRITE is sent to the HT bus, and waits for the HT bus to respond before returning to the AXI bus.
Offset: 0xd0
Reset value: 0x00000000
Name: HT bus POST address window 0 enable (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31
ht_post0_en
1
0x0
R / W HT bus POST address window 0, enable signal
30:23 Reserved
15
0x0
Keep
15: 0
ht_post0_trans
[39:24]
16
0x0
R / W HT bus POST address window 0, the translated address
[39:24]
Offset: 0xd4
Reset value: 0x00000000
Name: HT bus POST address window 0 base address (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31:16 ht_post0_base
[39:24]
16
0x0
R / W HT bus POST address window 0, address base address [39:24]
15: 0
ht_post0_mask
[39:24]
16
0x0
R / W HT bus POST address window 0, address masked [39:24]
Offset: 0xd8
Reset value: 0x00000000
Name: HT bus POST address window 1 enable (internal access)
Bit field
Bit field name
Bit width reset value Visit description
93
Page 106
Godson 3A1000 Processor User Manual Part 1
Bit field
Bit field name
Bit width reset value Visit description
31
ht_post1_en
1
0x0
R / W HT bus POST address window 1, enable signal
30:23 Reserved
15
0x0
Keep
15: 0
ht_post1_trans
[39:24]
16
0x0
R / W HT bus POST address window 1, the translated address
[39:24]
Offset: 0xdc
Reset value: 0x00000000
Name: HT bus POST address window 1 base address (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31:16 ht_post1_base
[39:24]
16
0x0
R / W HT bus POST address window 1, address base address [39:24]
15: 0
ht_post1_mask
[39:24]
16
0x0
R / W HT bus POST address window 1, address masked [39:24]
9.5.12
Prefetch address window configuration register
The address window hit formula in this controller is as follows:
hit = (BASE & MASK) == (ADDR & MASK)
It is worth mentioning that when configuring the address window register, the high bit of MASK should be all 1s and the low bit should be all 0s. 0 in MASK
The actual number of bits indicates the size of the address window.