4/29/2020
Godson 3A1000 Processor User Manual
87
[53:24], for LS3A1000D and below, [29:23]
Fixed at 0
Offset: 0xf4
Reset value: 0x00000000
Name: HT bus Uncache address window 0 base address (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31:16 ht_uncache0_
base [39:24]
16
0x0
R / W HT bus uncache address window 0, address base address
[39:24]
15: 0
ht_uncache0_
mask [39:24]
16
0x0
R / W HT bus uncache address window 0, address masked
[39:24]
Offset: 0xf8
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Godson 3A1000 Processor User Manual Part 1
Reset value: 0x00000000
Name: HT bus Uncache address window 1 is enabled (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31
ht_uncache1_en
1
0x0
R / W HT bus uncache address window 1, enable signal
30
ht_uncache1_
trans_en
1
0x0
R / W HT bus uncache address window 1, mapping enable signal
29: 0
ht_uncache1_
trans [53:24]
16
0x0
R / W HT bus uncache address window 1, the translated address
[53:24], for LS3A1000D and below, [29:23]
Fixed at 0
Offset: 0xfc
Reset value: 0x00000000
Name: HT bus Uncache address window 1 base address (internal access)
Bit field
Bit field name
Bit width reset value Visit description
31:16 ht_uncache1_
base [39:24]
16
0x0
R / W HT bus uncache address window 1, address base address
[39:24]
15: 0
ht_uncache1_
mask [39:24]
16
0x0
R / W HT bus uncache address window 1, address masked
[39:24]
9.5.14
HyperTransport bus configuration space access method
The protocol of the HyperTransport interface software layer is basically the same as the PCI protocol. Configuration access is directly related to the underlying protocol
Off, the method of access may be slightly different. As shown in Table 9-5, the configuration access space is located at the address
0xFD_FE00_0000 to 0xFD_FFFF_FFFFh. For configuration access in the PCI protocol, in Loongson No. 3, such as
The next realization.
Type 0:
Type 1:
Figure 9-1 HT protocol configuration access in Loongson 3
9.6 HyperTransport multiprocessor support
Loongson No. 3 processor uses HyperTransport interface for multi-processor interconnection, and can automatically maintain 4 hardware
Consistency request between chips. The following provides two multiprocessor interconnection methods:
Four piece Loongson No. 3 interconnection structure
The four CPUs are connected in pairs to form a ring structure. Each CPU uses two 8-bit controllers of HT0 to connect with two adjacent chips,
Among them, HTx_LO is the master device, and HTx_HI is the slave device, and the interconnection structure as shown below is obtained:
96
