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Godson 3A1000 Processor User Manual
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8 DDR2 / 3 SDRAM controller configuration
The design of the integrated memory controller inside Loongson No. 3 processor complies with the industry standard of DDR2 / 3 SDRAM (JESD79-2
And JESD79-3). In the Godson 3 processor, all memory read / write operations are implemented in compliance with JESD79-2B and
The provisions of JESD79-3.
8.1 Overview of DDR2 / 3 SDRAM controller functions
Loongson No. 3 processor supports a maximum of 4 CS (implemented by 4 DDR2 SDRAM chip select signals, that is, two double-sided memory
Article), contains a total of 18-bit address bus (ie: 15-bit row and column address bus and 3-bit logical Bank bus).
When Loongson No. 3 processor chooses to use different memory chip types, it can adjust the DDR2 / 3 controller parameter settings
To support. Among them, the maximum number of chip selects (CS_n) supported is 4, the number of row addresses (RAS_n) is 15, and the column addresses
The number of (CAS_n) is 14, and the number of logical body selection (BANK_n) is 3. The maximum supported address space is 128GB (237).
The physical address of the memory request sent by the CPU will be converted according to the method shown in the figure below:
Taking the 4GB address space as an example, follow the configuration below:
Chip select = 4 Bank number = 8
Number of row addresses = 12 Number of column addresses = 12
Figure 8-1 Conversion of DDR2 SDRAM row and column addresses and CPU physical addresses
The memory control circuit integrated in the Loongson 3 processor only accepts memory read / write requests from the processor or external devices
Demand, in all memory read / write operations, the memory control circuit is in the slave state.
The memory controller in Loongson No. 3 processor has the following characteristics:
● Full pipeline operation of commands and read and write data on the interface
● Memory commands are combined and sorted to improve overall bandwidth
● Configure register read and write ports, you can modify the basic parameters of the memory device
● Built-in dynamic delay compensation circuit (DCC) for reliable transmission and reception of data
● The ECC function can detect 1-bit and 2-bit errors on the data path, and can automatically detect 1-bit errors.
Error correction
● Support 133-400MHZ working frequency
8.2 DDR2 / 3 SDRAM read operation protocol
The protocol of DDR2 / 3 SDRAM read operation is shown in Figure 11-2. In the figure, the command (Command, CMD for short) consists of
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RAS_n, CAS_n and WE_n are composed of three signals. For read operations, RAS_n = 1, CAS_n = 0, and WE_n = 1.
Figure 8-2 DDR2 SDRAM read operation protocol
