4/29/2020
Godson 3A1000 Processor User Manual
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Make GS464 the processor IP including secondary cache; you can also connect multiple GS464 through AXI network and
Multiple secondary cache modules form an on-chip multi-processor CMP structure. The main features of the secondary cache module include:
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Using 128-bit AXI interface.
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8 items Cache access queue.
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Keywords first.
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The fastest read is 8 beats from receiving a read invalid request to returning data.
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Support Cache consistency protocol through the directory.
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It can be used for on-chip multi-core structure, and can also be directly connected with single processor IP.
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The soft IP level can be configured with the size of the secondary cache (512KB / 1MB).
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The four-way group connection structure is adopted.
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It can be closed dynamically during operation.
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Support ECC check.
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Support DMA consistent read and write and prefetch reading.
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Support 16 kinds of second-level cache hashes.
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Support to lock secondary cache by window.
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Ensure that read data returns atomicity.
The secondary cache module includes the secondary cache management module scachemanage and the secondary cache access module
scacheaccess. The Scachemanage module is responsible for processor access requests from the processor and DMA, while the secondary cache
The TAG, directory and data are stored in the scacheaccess module. In order to reduce power consumption, the TAG of the secondary cache,
The directory and data can be accessed separately. The secondary cache status bit and w bit are stored with TAG, and TAG is stored in TAG RAM
In, the directory is stored in DIR RAM, and the data is stored in DATA RAM. Invalid request to access secondary cache while reading
The TAG, directory and data of all channels are output, and the data and directory are selected according to the TAG. Replace request, refill request and write back
Request to operate only TAG, directory and data of all the way.
In order to improve the performance of some specific computing tasks, the secondary cache adds a locking mechanism. Level 2 in the locked area
The Cache block will be locked, so it will not be replaced by the secondary cache (unless the four-way secondary cache is locked
Piece). Four groups of lock window registers inside the secondary cache module can be dynamically configured through confbus, but must be
Ensure that one of the four secondary caches is locked. The size of each group of windows can be adjusted according to the mask, but not
Can exceed 3/4 of the size of the entire secondary cache. In addition, when the secondary cache receives the DMA write request, if the written area
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Godson 3A1000 Processor User Manual Part 1
If it is hit and locked in the secondary cache, the DMA write will be directly written to the secondary cache instead of memory.
Table 4-1 Secondary Cache Lock Window Register Configuration
name
address
Bit field
description
Slock0_valid
0x3ff00200
[63:63] Lock window 0 valid bits
Slock0_addr
0x3ff00200
[47: 0] No. 0 lock window lock address
Slock0_mask
0x3ff00240
[47: 0] No. 0 lock window mask
Slock1_valid
0x3ff00208
[63:63] Lock window 1 valid bit
Slock1_addr
0x3ff00208
[47: 0] No. 1 lock window lock address
Slock1_mask
0x3ff00248
[47: 0] No. 1 lock window mask
Slock2_valid
0x3ff00210
[63:63] Lock window 2 valid bits
Slock2_addr
0x3ff00210
[47: 0] No. 2 lock window lock address
Slock2_mask
0x3ff00250
[47: 0] No. 2 lock window mask
Slock3_valid
0x3ff00218
[63:63] Lock window 3 valid bits
Slock3_addr
0x3ff00218
[47: 0] No. 3 lock window lock address
Slock3_mask
0x3ff00258
[47: 0] No. 3 lock window mask
