4/29/2020
Godson 3A1000 Processor User Manual
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9.4.2
Internal window configuration of HyperTransport controller
Godson 3 processor HyperTransport interface provides a variety of rich address windows for users to use, including
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Godson 3A1000 Processor User Manual Part 1
As follows:
Table 9-6 Address window provided in HyperTransport interface of Loongson 3 processor
Address window
Window number accept bus
effect
Remarks
Receive window
(See window configuration
9.5.4)
3
HyperTransport
Determine whether to receive
HyperTransport
Visits sent on the bus
ask.
When in main bridge mode (ie configuration register
Act_as_slave is 0), only falls in
Access in these address windows will be internal
The bus responds, other visits will be recognized
Send back for P2P access
HyperTransport bus; in the design
When in standby mode (that is, in the configuration register
act_as_slave is 1), only falls here
Access in these address windows will be
Received and processed by the line, other visits will be
According to the agreement to return an error.
Post window
(See window configuration
9.5.8)
2
Internal bus
Determine if it will be internal
total
line
Correct
HyperTransport
Bus write access
Post Write
External write visits that fall in these address spaces
Question will be as Post Write.
Post Write: HyperTransport protocol
In this kind of write access does not need to wait for writing
In response, that is, the controller sends to the bus
After this write access will enter the processor
Row write access complete response.
Prefetch window
(See window configuration
9.5.9)
2
Internal bus
Determine whether to receive
Department ’s Cache access,
Fetch access.
When the processor cores are executed out of order, the total
Issue some guess read access or fetch
Access, this access for some IO space
it is wrong. By default, this
Access to the HT controller will return directly without
Visit the HyperTransport bus
ask. Through these windows you can enable
This type of access to the HyperTransport bus
ask.
Uncache window
(See window configuration
Section 9.5.10)
2
HyperTransport
Determine whether to
HyperTransport
Access operations on the bus
For internal
Uncache access
IO DMA inside Loongson 3 processor
Access, in the case of Cache side
Access is determined by the secondary cache
In order to maintain its IO consistency information.
And through the configuration of these windows, you can make
Access hits in these windows
Uncache way to directly access memory,
Without maintaining its IO consistency letter through hardware
interest.
9.5 Configuration Register
The configuration register module is mainly used to control the configuration register access from the AXI SLAVE terminal or the HT RECEIVER terminal.
Question, external interrupt processing, and save a lot of configuration registers visible in the software to control various working modes of the system.
First, the access and storage of configuration registers used to control various behaviors of the HT controller are in this module
The address of the access offset is 0xFD_FB00_0000 to 0xFD_FBFF_FFFF on the AXI side. All software in this module is visible
The registers are shown in the following table:
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