4/29/2020
Godson 3A1000 Processor User Manual
23
0x0000_0000_1000_0000
0x0000_0000_2000_0000
Low-speed I / O (PCI, etc.)
2.6 Chip configuration and sampling register
The chip configuration register (Chip_config) and chip sampling register (chip_sample) in Godson 3 provide
A mechanism to read and write the configuration of the chip.
Table 2-10 Chip Configuration Register (Physical Address 0x1fe00180)
Bit field
Field name
access
Reset value
description
2: 0
Freq_scale_ctrl
RW
3'b111
Processor core frequency division
The actual frequency of the processor core is
PLL frequency * (Freq_sca 1) / 8
3 DDR_Clksel_en
RW
1'b0
Whether to use software to configure DDR frequency multiplication
1: Use software configuration
0: use pin CLKSEL configuration
8 Disable_ddr2_confspace
RW
1'b0
Whether to disable the DDR configuration space
1: Disabled
0: Do not disable
9 DDR_buffer_cpu
RW
1'b0
Whether to open DDR read access buffer
1: open
0: disabled
12 Core0_en
RW
1'b1
Whether to enable processor core 0
1: open
0: disabled
13 Core1_en
RW
1'b1
Whether to enable processor core 1
1: open
0: disabled
14 Core2_en
RW
1'b1
Whether to enable processor core 2
1: open
0: disabled
15 Core3_en
RW
1'b1
Whether to enable processor core 3
1: open
0: disabled
16 Mc0_en
RW
1'b1
Whether to enable DDR controller 0
1: open
16
Page 29
Godson 3A1000 Processor User Manual Part 1
0: disabled
17 Mc1_en
RW
1'b1
Whether to enable DDR controller 1
1: open
0: disabled
18 DDR_reset0
RW
1'b1
Software reset DDR controller 0
1: Reset
0: Unreset
19 DDR_reset1
RW
1'b1
Software reset DDR controller 1
1: Reset
0: Unreset
22 HT0_en
RW
1'b1
Whether to enable the HT controller 0
1: open
0: disabled
23 HT1_en
RW
1'b1
Whether to enable the HT controller 1
1: open
0: disabled
28:24 DDR_Clksel
RW
5'b11111
Software configuration DDR clock multiplier relationship (when
(Valid when DDR_Clksel_en is 1)
