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Godson 3A1000 Processor User Manual
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The PCI / PCIX arbiter implements two-level round robin arbitration, bus docking, and isolation of damaged master devices. Its configuration and status
See PXArb_Config and PXArb_Status registers. The assignment of PCI / PCIX bus request and response lines is shown in Table 13-3.
Table 10-3 PCI / PCIX bus request and response line assignment
Request and answer line
description
0
Internal integrated PCI / PCIX controller
7: 1
External request 6 ~ 0
The rotation-based arbitration algorithm provides two levels, and the second level as a whole is scheduled as a member of the first level. Dangduo
When a device applies for the bus at the same time, the first level device is rotated once, and the highest priority device in the second level can get
line.
The arbiter is designed to be switched at any time as long as conditions permit. For some PCI devices that do not conform to the protocol,
Doing so may make it abnormal. Using mandatory priority allows these devices to occupy the bus through continuous requests.
Bus docking refers to whether or not to select one to give an enable signal when no device requests to use the bus. For already
As far as allowed devices are concerned, directly initiating bus operations can improve efficiency. Loongson 2F's PCI arbiter provides two kinds of stop
By mode: the last master device and the default master device. If you cannot dock in special occasions, you can set the arbiter
To dock to the default No. 0 master device (internal controller), and rely on delay 0.
10.2 LPC controller
The LPC controller has the following characteristics:
● Conform to LPC1.1 specification
● Support LPC access timeout counter
● Supports Memory Read and Memory write access types
● Support Firmware Memory Read, Firmware Memory Write access type (single byte)
● Supports I / O read and I / O write access types
● Support memory access type address conversion
● Support Serizlized IRQ specification, provide 17 interrupt sources
The address space distribution of LPC controller is shown in Table 4:
Table 10-4 LPC Controller Address Space Distribution
Address name
Address range
size
LPC Boot
0X1FC0_0000-0X1FD0_0000
1MByte
103
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LPC Memory
0X1C00_0000-0X1E00_0000
32MByte
LPC I / O
0X1FF0_0000-0X1FF1_0000
64KByte
LPC Register
0X1FE0_0200-0X1FE0_0300
256Byte
The LPC Boot address space is the address space that the processor first accesses when the system starts. This address space supports LPC
Memory or Firmware Memory access type. What type of access is issued by the system at startup
LPC_ROM_INTEL pin control. LPC Firmware Memory is issued when the LPC_ROM_INTEL pin is pulled up
Access, LPC Memory access type is issued when the LPC_ROM_INTEL pin is pulled down.
The LPC Memory address space is the address space accessed by the system with Memory / Firmware Memory. LPC control
The type of memory access issued by the controller is determined by the configuration register LPC_MEM_IS_FWH of the LPC controller.
The address sent by the processor to this address space can perform address translation. The converted address is sent by the configuration of the LPC controller
Register LPC_MEM_TRANS.
The processor's access to the LPC I / O address space is sent to the LPC bus according to the LPC I / O access type. Address is address
The space is 16 bits lower.
There are three 32-bit registers in the LPC controller configuration register. The meaning of the configuration register is shown in Table 13-5:
