LG 50PC1DR - - 50" Plasma TV, Training Manual

Page: 33 / 138

Plasma Training
33
Adjustments
CIRCUIT DESCRIPTIONS
/RESET
CS8415A
EEPROMEEPROM
BSS83
BSS83
MUX
CPLD
(XC95144XL)
LGDT350
2
POD/OOB Controller
V
ideo
In/Out
V
ideo
In/Out
Side
A
V_2
V
,LR
3
Rear
A
V_1
V,
L
R
3
Rear
S_1
YC
2
Side
S_2
YC
2
MNT_V_Out
M_MSP
4440
Ext_
Audio
LR
2
IN1
OUT2 OUT1
OUT1
TV
IN4
IN1 IN4
IN5
OUT3
RGB-
P
C
5
RGBHV
Comp_1
YCbCr
3
Comp_2
YCbCr
3
uCom
(M37151)
IN2 IN3 IN4
CXA2069
Comp_1
LR
2
NT
T
uner
OR1
656
Dat
a[0:7]
CLK
9
TP/D1
9
OR3
2
YCbCr
16
H,V
,CLK
3
FID
OR1 OR2
YCbCr
24
H,V
,CLK
3
FID
V
ideo
Decoder
(UPD6401
1)
X-t
a
l
(24.576M)
System
CPLD1
(XC95288XL)
H,V
,CLAMP
H,V
Active
LPF
(FMS6407)
ADC
(AD9883A)
FID
3
LPF LPF
HV_PC
HV_pol
OR1
YCbCr
24
H,V
,
CLK
3
2
3
YCbCr
OR2
NTSC
T
uner
(T
AUM
-H501P) A
TSC/NTSC
T
uner
(TDVS-
H701F)
V
RF
SW
Cable
ANT
.
1.8V
Reg.
V
IF_AGC
2
nd
IF
±
(6M)
U-
Com
SIF
/RESET
X-
ta
l
(25M)
OOB
T
uner
(T
AEU
-H015P)
POD
1394
Controller
(TSB43DA42)
(TP
A
±
,TPB
±
)*
2
4
D
OOB
IF+/
-
PI
PO
8
8
8
Add.
[0:13]
14
DRX
/
CRX
2
POD_TP[0:7] CLK,V
ALID,SOP
KIA7029
74LCX24
4
Reset
HV
,Hact
RGB
30
3
DOutClk
L
VDS
Tx
.
(THC63L
VD103)
TX[0:4]
¡¾
TXC
¡¾
12
VCXO 27Mhz
LGDPLL
(LGDT1901
A)
HD2_VDPClk
(74.25M)
HD2_SYS_CLK
FR_60
RS-232C
(ST3232)
RX_HDMI_SPDIF
MUX
(74LCX15
7)
SPDIF
Out
SPDIF
In1(DVI)
SPDIF
In2(DVD)
SPDIF_BYP
ASS_SEL
System
CPLD1
(XC95288XL)
I2C
Hub
(PCA951
6)
IIC
A
EN[0:3(GPIO)]
4
OR4
CPU
[PPC
405GPr]
-
SDRAM
Controller
-
Peripheral
Controller
-
Local
BUS
I/F
-
Serial(2),
GPIO,
I2Cr
(PY2DR
-
PX4DR)
PDP
DVR
BLOCK
(PY2DR
-
PX4DR)
PDP
DVR
BLOCK
1.8V
Reg.
EEPROM
(A
T24LC512)
V
olt
age
Controller
L
TC1470
VPP_SW VPP_SW
Flag
VPP1
MNT_Out
LR
2
SIF
LR
2
Comp_2
LR
2
RGB(Phone)
LR
2
I2S
Out
3
HD-
II
HD-
II
ANALOG_L/R
BSS83
BSS83
8
2
RXD[0:2]
¡¾
,
RXCLK
¡¾
DDC(I2C)
RGB H,V
,
CLK
3
24
HD2_MAIN_PWM
OR4
OR4
RX_HDMI_SPDIF
IEP
LGDP441
0
SPDIF_IN_BYP
ASS
AUDIO
ADC
(CS5331)
I2S
In
3
PWM
MODULA
T
O
R
(NSP6241B)
I2S I2S_MCLK
PWM
AMP
(T
AS5122)
PWM_L/R
CXA2069
MAIN_CVBS
SYNC
SEP
ARA
T
O
R
(MM1
108XF)
ANALOG
DE/
MUL
TIPLEXER
(74HCT4053)
U-
COM
(PIC18F1220)
H,V
G_LINK_CONN
UAR
T1_RX/TX
GEM_IR_OUT
V
olt
age
Comp.
(LM31
1M)
AH_SPD
IFCLK
HD2_DAC
SCK/LRCK
Buffer
(74LCX244)
3 I2S
Out
BUFFER
(MC33078
)
Sil9021
IIC
B
0
¡¿
20
IIC
A
0
¡¿
C
0
IIC
A
0
¡¿
C2
IIC
A
0
¡¿
C
6
IIC
C
0
¡¿
BA
IIC
C
0
¡¿
B8
IIC
C
0
¡¿
98
IIC
D
0
¡¿
1C
IIC
C
0
¡¿
A6
IIC
C
0
¡¿
1e
IIC
D
0
¡¿
2C
IIC
C
0
¡¿
60,68,74
IIC
B
0
¡¿
90
2
11
IIC
B
IIC
C
IIC
D
M_MSP
4440
M_MSP
4440
SIF
IIC
B
0
¡¿
84
V
ideo
SW
(CXA2181
)
EPF_RGB-
P
C
RGBHV
5
IN1
A
T/NT
T
uner
Main
Sound
Proc
(MSP4440)
IIC
D
0
¡¿
8
0
Sub
MSP444
0
NT
T
uner
Rear
L/R
Side
L/R
EPF_L/R
I2S
(Main)
(Sub)
244 Buf
.
PDR CLK
1394_OUT_TP[0:7
]
1394_IN_TP[0:7
]
TP_ENC[0:7
]
KFIR-
II
TPN
-II
(LGDT1303)
TPN _TP [0 :7 ]
PDR_PES[0:7
]
HD 2_TP [0:7 ]
TP_V1[0:7
]
KFIR
-I
I
(BCM7040)
TPN-
II
/
MUX
CPLD
TP_ENC[0:7]
KFIR
-I
I
TP_ENC[0:7]
HD-II
(V
er2.2)
-TP
D
e
-Mux
-
MPEG
Decoding
:
MP@HL
-Format
Converter
-Host
I/F
,
Memory
I/F
-Digit
al
I/F
-V
ideo
DAC,
NTSC
Encoder
-A
C
-3
Decoder/SPDIF
In/out
CY2305S
C
HD2_NT2CLK TPN_SYS_CLK EPLD_CLK
DPLL_R[1:3]
HD2_ICE958_OUT
SPDIF
Receiver
.
(CS8415A)
XDR_DA
T
A_R/G/B[0:9]
244
Buf
.
KFIR
-I
I
Sub
MSP4440
SDRAM
32MByte
(8MB
x4)
Peripheral
Bus
64
-Bit
I/F
Control
GPIO
Peripheral
Bus
SDRAM
(4Mx16Bit)
SDRAM
(2Mx
32Bit)
SA
T
A
I/F
(SiI3512)
X-
ta
l
(25M)
TX/RX
P1,N1
TX/RX
P2,N2
PCI
Bus
PCI
Bus
PCI
Bus
IIC
D
0
¡¿
50
IIC
D
0
¡¿
88
VBI
Slicer
&
IR
(USA
Only)
OOB/POD
Controller
Flash
Memory
16MB(8MBx2)
32Bit
Bus
I/F
IN3 IN6
HD2_REC_CVBS
CXA2069
EPF_L/R
A/V
SW
(CXA2069)
HD2_CVBS_OUT
HD-
II
SDRAM
64MB(32MBx2)
PWM
AMP
(T
AS5122)
LGDT3701
+3.3V
VSB
DA
T
A
11
Filter
(FMS6410)
Filter
(FMS6410)
2
2
SDRAM
(1Mx
16Bit)
V
ideo
Decoder
(UPD6401
1)
X-t
a
l
(24.576M
)
SDRAM
(1Mx
16Bit)
2
IIC
A
IIC
B
IIC
C
IIC
D
8
RXD[0:2]
¡¾
,
RXCLK
¡¾
DDC(I2C)
EEPROMEEPROM
HDMI
Rx
SiI
9021
LGDP441
1
PIC18F242
CPU