LG 50PC1DR - - 50" Plasma TV, Training Manual

Page: 32 / 138

CIRCUIT DESCRIPTIONS
Plasma Training
32
Adjustments
MUX
CPLD
(XC95144XL)
LGDT3502
POD/OOB Controller
V
ideo
In/Out
V
ideo
In/Out
Side
A
V_4
V
,LR
3
Rear
A
V_1
V,
L
R
3
Rear
S_1
YC
2
Side
S_4
YC
2
MNT_V_Out
M_MSP
4440
Ext_
Audio
LR
2
IN1
OUT2
OUT1
OUT1
TV
IN4
IN1
IN4
IN5
OUT3
RGB-
P
C
5
RGBHV
Comp_1
YCbCr
3
Comp_2
YCbCr
3
uCom
(M37151)
IN2
IN3
IN4
CXA2069
Comp_1
LR
2
NT
T
uner
OR1
V
ideo
Decoder
+3D
Comb
(uPD6401
1A)
656
Dat
a[0:7]
CLK
9
TP/D1
9
OR3
X-t
a
l
(24.576M)
YCbCr
16
H,V
,CLK
3
FID
OR1 OR2
YCbCr
24
H,V
,CLK
3
FID
V
ideo
Decoder
+3D
Comb
(uPD6401
1A)
X-t
a
l
(24.576M
)
System
CPLD1
(XC95288XL)
H,V
,CLAMP
H,V
Active
LPF
(6/38MHz)
ADC
(AD9883A)
FID
3
LPF LPF
HV_PC
HV_pol
OR1
YCbCr
24
H,V
,
CLK
3
2
3
YCbCr
OR2
NTSC
T
uner
(T
AFM
-H103P)
A
TSC/NTSC
T
uner
(TDVS-
H701P)
PVSB/OOB
(LGDT3701)
V
RF
SW
Cable
ANT
.
1.8V Reg.
V
IF_AGC
2
nd
IF
±
(
6M
)
U-
Com
SIF
Reset
X-t
a
l
(M)
OOB
T
uner
(T
AEU
-H015P)
POD
1394
Controller
(TSB43DA42)
(TP
A
±
,TPB
±
)*
2
4
D
OOB
IF+/
-
PI
PO
8
8
8
14
VSB_DA
T
A
11
POD_TP[0:7]
LK,V
ALID,SOP
KIA7029
74LCX244
Reset
HV
,Hact
RGB
30
3
DOutClk
L
VDS
Tx
.
(THC63L
VD103)
12
VCXO
27Mhz
LGDPLL
(LGDT1901A)
HD2_VDPClk
(74.25M)
HD2_SYS_CLK
FR_60
RS-232C
(ST3232)
RX_HDMI_SPDIF
MUX
(74LCX157)
SPDIF
Out
SPDIF
In1(DVI)
SPDIF
In2(DVD)
SPDIF_BYPASS_SEL
System
CPLD1
(XC95288XL)
I2C
Hub
(PCA9516)
IIC
A
EN[0:3(GPIO)]
4
OR4
CPU
[PPC
405GPr]
-
SDRAM
Controller
-
Peripheral
Controller
-
Local
BUS
I/F
-
Serial(2),
GPIO,
I2Cr
PX4D
PDP
BLOCK
PX4D
PDP
BLOCK
1.8V Reg.
EEPROM
(A
T24LC512)
V
olt
age
Controller
L
TC1470
VPP_SW
Flag
VPP1
MNT_Out
LR
2
SIF
LR
2
Comp_2
LR
2
RGB(Phone)
LR
2
I2S
Out
3
HD-
II
HD-
II
ANALOG_L/R
HDMI
Rx
SiL
9021
BSS83
BSS83
8
2
RXD[0:2]
¡¾
,
RXCLK
¡¾
DDC(I2C)
RGB H,V
,
CLK
3
24
EEPRO
M
HD2_MAIN_PWM
OR4
OR4
HDMI
1
CS8415A
RX_HDMI SPDIF
IEP
LGDT4410
SPDIF_IN_BYP
ASS
AUDIO
ADC
(CS5331)
I2S
In
3
PWM
MODULA
T
O
R
(NSP2100A)
I2S I2S_MCLK
PWM
AMP
(T
AS5122)
PWM_L/R
CXA2069
Sub_CVBS
SYNC
SEP
ARA
T
O
R
(MM1
108XF)
ANALOG
DE/
MUL
TIPLEXER
(74HCT4053)
Slicer
U-
COM
(PIC18F1220
)
H,V
G_LINK_CONN
GLink
GEM_IR_OUT
V
olt
age
Comp.
(LM31
1M)
AH_SPDIFCLK
HD2_DAC_SCK/LRCK
Buffer
(74LCX244)
3
I2S Out
BUFFER
(MC33078)
Sil9021
IIC
B
0
¡¿
20
IIC
A
0
¡¿
C0
IIC
A
0
¡¿
C2
IIC
A
0
¡¿
C6
IIC
C
0
¡¿
8A
IIC
C
0
¡¿
B8
IIC
C
0
¡¿
98
IIC
D
0
¡¿
1C
IIC
C
0
¡¿
AE
IIC
C
0
¡¿
1E
IIC
D
0
¡¿
CC
IIC
C
0
¡¿
60,68
IIC
D
0
¡¿
90
2
11
IIC
B
IIC
C
IIC
D
MSP 4440
MSP 4440
SIF
IIC
D
0
¡¿
84
V
ideo
SW
(CXA2181
)
EPF_RGB-
P
C
RGBHV
5
IN1
A
T/NT
T
uner
Sound
Proc
(MSP4440)
IIC
D
0
¡¿
80
Main
Sub
1394_OUT_TP[0:7
]
1394_IN_TP[0:7
]
HD2_TP [0:7]
HD-II
(V
er2.2)
-TP
D
e
-Mux
-
MPEG
Decoding
:
MP@HL
-Format
Converter
-Host
I/F
,
Memory
I/F
-Digit
al
I/F
-V
ideo
DAC,
NTSC
Encoder
-A
C
-3
Decoder/SPDIF
In/out
CY2305SC
HD2_NT2CLK TPN_SYS_CLK EPLD_CLK
DPLL_R[1:3]
HD2_ICE958_OUT
SPDIF
Receiver
.
(CS8415A)
XDR_DA
T
A_R/G/B[0:9]
Peripheral
Bus
64
-Bit
I/F
Control
GPIO
Peripheral
Bus
SA
T
A
I/F
(SiI3512)
X-
ta
l
(25M)
TX/RX
P1,N1
TX/RX
P2,N2
PC`I
Bus
PCI
Bus
IIC
D
0
¡¿
50
Gemst
ar
VBI
Slicer
&
IR
CKT
Flash
Memory
16MB(8MBx2)
32Bit
Bus
I/F
IN3 IN6
EPF_L/R
A/V
SW
(CXA2069)
HD2_CVBS_OUT
HD
-II
SDRAM
64MB(32MBx2)
IR
U-
COM
(PIC18F242)
Slicer
Dat
a
IIC
B
0
¡¿
58
IIC
C
0
¡¿
1C
SDRAM
32MByte
(8MB
x4)
SDRAM
2MB
BSS83
BSS83
RXD[0:2]
¡¾
,
RXCLK
¡¾
DDC(I2C)
8
2
EEPRO
M
HDMI
2
2
CRX DRX
CableCARD
circuit