QSEVEN-Q7AL - Rev.1.0
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System Resources
Peripheral Component Interconnect (PCI) Devices
6.1.
All devices follow the Peripheral Component Interconnect (PCI) 2.3 and PCI Express Base 1.0a specification. The BIOS
and Operating System (OS) control the memory and I/O resources. For more information, refer to the PCI 2.3
specification.
I2C Bus
6.2.
The following table specifies the devices connected the I2C bus including the I2C address.
Table 7: I2C Bus Port Address
8-bit I2C Address
Used For
Available
Comment
A0h
JIDA-EEPROM
Yes
Module EEPROM
C0h
LVDS PTN3460
Yes
LVDS EEPROM
System Management (SM) Bus
6.3.
The 8-bit SMBus address uses the LSB (Bit 0) for the direction of the device.
Bit0 = 0 defines the write address
Bit0 = 1 defines the read address
The 8-bit address listed below shows the write address for all devices. The7-bit SMBus address shows the device
address without bit0.
Table 8: SMBus Address
8-bit
Address
7-bit
Address
Device
Comment
SMBus
5Ch
2eh
HWM NCT7802Y
Do not use under any circumstances
SMB
A0h
50h
SPD DDR Channel 1 (SO-DIMM)
SMB
30h
18h
SO-DIMM Thermal Sensor
If available on the used memory-module SMB
