QSEVEN-Q7AL - Rev.1.0
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5/
Features and Interfaces
LPC
5.1.
The Low Pin Count (LPC) Interface signals are connected to the LPC bus bridge located in the CPU or integrated
chipset. The LPC low speed interface can be used for peripheral circuits such as an external Super I/O controller that
typically combines legacy-device support into a single IC. The implementation of this subsystem complies with the
QSEVEN® Specification.
The LPC bus does not support DMA (Direct Memory Access). When more than one device is used on LPC, a zero delay
clock buffer is required that can lead to limitations for the ISA bus.
Table 3: Supported BIOS Features
Interface Signals
PS/2
Not supported
UART
Supported as COM0 only (on CPLD *SoC optional)
LPT
Not supported
Floppy
Not supported
GPIO
Supported
CAN
Supported
I2C
Supported
Features marked as not supported do not exclude OS support (e.g. Hardware Monitor ( HWM) is accessible via SMB). If
any other LPC Super I/O additional BIOS implementations are necessary, contact Kontron Support.
Serial Peripheral Interface (SPI)
5.2.
The Serial Peripheral Interface Bus (SPI bus) is a synchronous serial data link standard. Devices communicate in
master/slave mode, where the master device initiates the data frame. Multiple slave devices are allowed with
individual slave select (chip select) lines. SPI is sometimes called a four-wire serial bus, contrasting with three, two
and one-wire serial buses.
The SPI interface can only be used with a SPI flash device to boot from the external BIOS on
the baseboard.
SPI boot
5.3.
The Qseven-Q7AL supports boot from a 16 MB, 3.3 V serial external SPI Flash. Alternativly, the SPI Flash can be
configured to boot from either on-module SPI Flash or the on-carrierboard Flash pin (Module_BIOS_DIS#).
Table 4: SPI Boot Pin Configuration
Configuration
MODULE_BIOS_DIS# Function
1
Open
Boot on module BIOS
2
GND
Boot on carrierboard BIOS
