User’s and Service Guide U3047-90002
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U3047AE04
Service Information
Power Supply
The switching power supply (0950-4729) coverts the AC line voltages to DC. This is an
automatic line voltage selecting power supply. The DC supplies are connected to the test set
control board through four wire harness to J10, J11, J12 and J13. The 24 Vdc section of the
power supply is not used in this intrument.The AC line voltage (100 to 240 V @ 50/60 Hz) is
provided from the line module on the rear panel.
Source and Receiver Switch Paths
SW1 - Source to Ports (1 and 5) Switch 1 provides control of the Source Output path to PNA-X
Port 1 and Test Set Port 5. In the state shown in the block diagram, switch 1 routes the RF
Source back to the PNA-X Port 1, and the Test Set Source path to Port 5 is terminated.
SW3 - Source to Ports (3 and 6) Switch 3 provides control of the Source Output path to PNA-X
Port 3 and Test Set Port 6. In the state shown in the block diagram, switch 3 routes the RF
Source back to the PNA-X Port 3, and the Test Set Source path to Ports 6 is terminated.
SW6 - Source to Ports (4 and 7) Switch 6 provides control of the Source Output path to PNA-X
Port 4 and Test Set Port 7. In the state shown in the block diagram, switch 6 routes the RF
Source back to the PNA-X Port 4, and the Test Set Source path to Ports 7 is terminated.
SW8 - Source to Ports (2 and 8) Switch 2 and 8 provide control of the Source Output path to
PNA-X Port 2 and Test Set Port 8 and 12. In the state shown in the block diagram, switch 13
routes the RF Source back to the PNA-X Port 2, and the Test Set Source path to Ports 8 and 12
are terminated.
SW2 - Receiver to Ports (1 and 5) Switch 2 provides control of the Receiver Input path to PNA-
X Port 1 and Test Set Port 5. In the state shown in the block diagram, switch 2 routes the Port 1
CPLR ARM to the Receiver, and Test Set Ports 5 CPLR ARM path is terminated.
SW4 - Receiver to Ports (3 and 6) Switch 7 and 8 provide control of the Receiver Input path to
PNA-X Port 3 and Test Set Ports 6. In the state shown in the block diagram, switch 4 routes the
Port 3 CPLR ARM to the Receiver, and Test Set Ports 6 CPLR ARM path is terminated.
SW5 - Receiver to Ports (4 and 7) Switch 11 and12 provide control of the Receiver Input path
to PNA-X Port 4 and Test Set Ports 7. In the state shown in the block diagram, switch 11 routes
the Port 4 CPLR ARM to the Receiver, and Test Set Ports 7 CPLR ARM path is terminated.
SW7 - Receiver to Ports (2 and 8) Switch 15 and 16 provide control of the Receiver and Input
path to PNA-X Port 2 and Test Set Port 8. In the state shown in the block diagram, switch 7
routes the Port 2 CPLR ARM to the Receiver, and Test Set Ports 8 CPLR ARM path is terminated.
