Figure 42.
Reverse Parallel Loopback Path
TX
Buffer
TX PMA
RX PMA
RX
Buffer
Loopback path
TX Data
Data Pattern
Generator
MUX
Serializer
TX EQ
RX EQ
Clock Recovery
Sampler
Data Pattern
Verifier
Deserializer
EHIP_LANE/
EHIP_CORE/
RS-FEC/
PMA Direct
Gray Encoder/
Pre-coder
NRZ/
PAM4
MUX
Gray/Pre-
decoding
NRZ/
PAM4
High S
peed C
lock
Error
Injector
Reverse parallel loopback path
Legend:
Related Information
•
on page 165
•
on page 170
3.1.5. PMA Interface
The PMA interface block contains the FIFO and the gearbox.
Note:
The gearbox feature is only enabled when using RS-FEC.
Figure 43.
TX Data Flow
Simplified blocks. The FIFO is indicated in the red box.
50/100GbE
& 1588
Core Interface
EMIB
FIFO
FIFO
10/25GbE
PMA Interface
FIFO
GB
PMA
Native PHY IP Core
MAC
Enc
Scr
PCS
Data from four
other channels
RS-FEC
Data from three
other channels
1588 signals
to/from two
other
channels
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
76