Intel Stratix 10 User Manual Download

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Figure 14.

Transceiver Design Flow

Connect Transceiver Datapath to MAC IP Core or to a data generator/analyzer

Create your own reset controller

Compile Design

Verify Design Functionality

Connect reset controller to the Native PHY IP core

(skip this step if you are using the Native PHY IP core’s reset controller)

Assign pins to top level I/O’s and modify IP Synopsys Design Constraints (.sdc)

file for the Native PHY IP core

Generate the Native PHY IP core

Configure the Native PHY IP core datapath,

reference clock, dynamic reconfiguration,

and reset controller options

Select E-Tile Native PHY IP core

2.1.1. E-Tile Native PHY IP Core

Much like the Intel Stratix 10 L- and H-Tile Native PHY IP Core, you have multiple

options when instantiating the IP:
•

Instantiating the Native PHY IP to interface to your own IP

•

Not instantiating the Native PHY IP as apart of your own IP, and instead, providing

a design example which contains both the MAC IP and the Native PHY IP instances

2.2. Configuring the Native PHY IP Core

The Intel Stratix 10 E-Tile Transceiver Native PHY IP core is the primary design entry

tool, and provides direct access to Intel Stratix 10 E-Tile transceiver PHY features.

2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices

UG-20056 | 2019.02.04

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Stratix

10 E-Tile Transceiver PHY User Guide

Summary of Contents for Stratix 10

Page 1: ...Intel Stratix 10 E Tile Transceiver PHY User Guide Subscribe Send Feedback UG 20056 2019 02 04 Latest document on the web PDF HTML ...

Page 2: ...arameters 27 2 2 2 PMA Parameters 29 2 2 3 Core Interface Options 33 2 2 4 PMA Interface 36 2 2 5 PMA Adaptation 37 2 2 6 Reed Solomon Forward Error Correction RS FEC Parameters 41 2 2 7 Reset Parameters 45 2 2 8 Dynamic Reconfiguration Parameters 46 2 2 9 Port Information 49 2 2 10 PLL Mode 52 2 3 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices Revision History 54 3 Intel Strat...

Page 3: ...5 6 8 Interfaces 117 6 8 1 Reset Parameters in the Native PHY GUI 117 6 8 2 HDL Ports Interfaces 117 6 9 Resetting Transceiver Channels Revision History 118 7 Dynamic Reconfiguration 119 7 1 Dynamically Reconfiguring Channel Blocks 120 7 2 Interacting with the Dynamic Reconfiguration Interface 120 7 3 Unsupported Features 121 7 4 Reading from the Dynamic Reconfiguration Interface 121 7 5 Writing t...

Page 4: ... 2 PMA Control and Status Registers 166 9 1 3 PMA AVMM Registers 167 9 2 PMA Attribute Codes 170 9 2 1 0x0001 PMA Enable Disable 170 9 2 2 0x0002 PMA PRBS Settings 171 9 2 3 0x0003 Data Comparison Set Up and Start Stop 172 9 2 4 0x0005 TX Channel Divide By Ratio 173 9 2 5 0x0006 RX Channel Divide By Ratio 173 9 2 6 0x0008 Internal or Serial Loopback and Reverse Parallel Loopback Control 174 9 2 7 ...

Page 5: ...9 5 21 rsfec_core_ecc_hold 205 9 5 22 rsfec_err_inj_tx 206 9 5 23 rsfec_err_val_tx 206 9 5 24 rsfec_corr_cw_cnt Low 207 9 5 25 rsfec_corr_cw_cnt High 207 9 5 26 rsfec_uncorr_cw_cnt Low 208 9 5 27 rsfec_uncorr_cw_cnt High 208 9 5 28 rsfec_corr_syms_cnt Low 208 9 5 29 rsfec_corr_syms_cnt High 209 9 5 30 rsfec_corr_0s_cnt Low 209 9 5 31 rsfec_corr_0s_cnt High 210 9 5 32 rsfec_corr_1s_cnt Low 210 9 5 ...

Page 6: ...oard 226 B 9 Debug Tools 227 B 9 1 Monitoring Transceiver Signals 227 B 10 PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation Revision History 228 Contents Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 6 ...

Page 7: ...es are connected to the FPGA fabric using Intel s Embedded Multi die Interconnect Bridge EMIB technology Related Information Intel Stratix 10 TX Advance Information Brief Intel Stratix 10 GX SX Device Overview Intel Stratix 10 L and H Tile Transceiver PHY User Guide 1 1 Supported Features Table 2 Features Supported in E Tile Transceivers Feature Description Total transceivers 24 dual mode channels...

Page 8: ...el Stratix 10 MX device configurations combine FPGAs with high bandwidth memory 1 2 1 Intel Stratix 10 TX H Tile and E Tile Configurations Intel Stratix 10 TX FPGAs offer transceiver capability by combining H Tiles and E Tiles This section lists all possible TX FPGA configurations Figure 1 Intel Stratix 10 TX Device with 1 E Tile and 1 H Tile 48 Transceiver Channels H Tile 24 Channels Package Subs...

Page 9: ...E Tile 24 Channels EMIB TX 2100 UF50 F2397 TX 2500 UF50 F2397 TX 2800 UF50 F2397 Figure 4 Intel Stratix 10 TX Device with 5 E Tiles and 1 H Tile 144 Transceiver Channels E Tile 24 Channels E Tile 24 Channels H Tile 24 Channels Package Substrate EMIB EMIB EMIB Core Fabric TX 2500 YF55 F2912 E Tile 24 Channels EMIB TX 2800 YF55 F2912 E Tile 24 Channels E Tile 24 Channels EMIB EMIB There is no packag...

Page 10: ...age migration between Intel Stratix 10 MX and Intel Stratix 10 TX device families H Tile and E Tile or Intel Stratix 10 GX SX device families 1 3 Transceiver Counts in Stratix 10 TX MX Devices Table 3 Transceiver Counts in Intel Stratix 10 TX Devices with E Tiles NF43 SF50 UF50 YF55 The number in the Intel Stratix 10 TX Device Name column indicates the device s Logic Element LE count in thousands ...

Page 11: ...UF55 55 mm x 55 mm Transceivers E H MX 1650 72 24 MX 2100 72 24 1 4 E Tile Building Blocks Intel Stratix 10 E Tile transceivers consist of the following individual blocks Transceiver channels Reference clock network Ethernet Hard IP EHIP_LANE EHIP_CORE Reed Solomon Forward Error Correction RS FEC 1 Intel Stratix 10 E Tile Transceiver PHY Overview UG 20056 2019 02 04 Send Feedback Intel Stratix 10 ...

Page 12: ...4 PMA CH5 PMA CH6 PMA CH7 PMA CH8 PMA CH9 PMA CH10 PMA CH11 FEC 528 514 or 544 514 Aggregate 100G Fractured 25G FEC 528 514 or 544 514 Aggregate 100G Fractured 25G EHIP_CORE 100G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_CORE 100G MAC PCS 6 7 8 9 10 11 8 9 10 11 6 7 6 7 6 7 4 5 6 7 2 3 4 5 0 1 2 3 0 1 8 9 10 11 ...

Page 13: ... about the reference clocks refer to the Clock Network chapter Related Information Clock Network on page 86 1 4 2 GXE Channel Usage Channel usage depends on your channel configuration In NRZ mode all 24 GXE channels in a tile are available When the channel is configured in PAM4 mode and the data rate is greater than 30 Gbps two adjacent core interfaces are combined to provide a single PAM4 channel...

Page 14: ...bps PAM4 PMA Direct Mode without RS FEC 12 even numbered channels are available in a tile when the data rate is greater than 30 Gbps 1 Intel Stratix 10 E Tile Transceiver PHY Overview UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 14 ...

Page 15: ...efault setting which includes source termination at 2 5 V and AC coupling caps The Intel Stratix 10 Device Datasheet provides the electrical characteristics under the E Tile section Additional important electrical information is available in the Intel Stratix 10 GX MX and SX Device Family Pin Connection Guidelines Table 5 Key Reference Clock Considerations Consideration Description Power The refer...

Page 16: ...put that receives one of the nine reference clocks refclk 8 0 The first refclk 0 is a low skew balanced clock and the other eight are non skew balanced clocks Only refclk 0 supports channel bonding which is used mainly for TX clocking When an RX channel is adjacent to a TX channel and is running at the same rate you can share any of the reference clocks between the two channels Each of the 24 chan...

Page 17: ...2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL The reference clock network spans across the entire transceiver tile If the design requires a single reference clock to be supplied to more than one transceiver tile you must route the reference clock to multiple tiles on the printed circuit board PCB 1 Intel Stratix 10 E Tile...

Page 18: ...vide by 2 LVPECL Transmitter Receiver Transmitter Receiver Transceiver Transceiver REFCLK Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL REFCLK_0 REFCLK_8 REFCLK_0 REFCLK_8 All 24 channels have access to all nine reference clock options This provides Full flexibility on selec...

Page 19: ... being used for TX and RX on both channels enabling use of the same reference clock Transmitter Receiver Channel 0 Unused Transmitter Receiver Channel 1 refclk 0 refclk 1 refclk_in_B refclk 8 2 refclk_in_B Related Information Intel Stratix 10 Device Datasheet Intel Stratix 10 Device Family Pin Connection Guidelines 1 4 4 Ethernet Hard IP EHIP The Ethernet Hard IP is a hardened core of assorted mul...

Page 20: ...gate Channels 16 17 Protocol Used for PTP EHIP_CORE RS FEC No Channels 18 19 Protocol Unused N A RS FEC N A Channels 20 21 22 23 Protocol 100GbE PAM4 EHIP_CORE RS FEC Yes 544 514 Aggregate The Intel Stratix 10 E Tile implementation of the Ethernet Hard IP provides the following features and support 4x hardened MACs per Intel Stratix 10 E Tile Each MAC block can be configured as One 100 GbE interfa...

Page 21: ... Feature L Tile H Tile E Tile Native PHY IP Configure NRZ mode Configure NRZ and PAM4 PLL IP ATXPLL fPLL and CMU PLL IPs available in the IP catalog Embedded in Native PHY and Ethernet Hard IPs Reset controller IP Reset controller IP available in the IP catalog Embedded in the Native PHY and Ethernet Hard IP cores Clocking modes TX PMA bonding up to 24 channels ATXPLL fPLL and fPLL fPLL cascade VC...

Page 22: ...njection Not available Available Eye viewer On Die Instrumentation through Transceiver Toolkit and Avalon MM AVMM access Eye viewer available only through Transceiver Toolkit 1 5 Intel Stratix 10 E Tile Transceiver PHY Overview Revision History Document Version Changes 2019 02 04 Made the following changes Updated figures in Intel Stratix 10 TX H Tile and E Tile Configurations Updated Transceiver ...

Page 23: ...tarates 30 GbpsPAM4 NRZ PMA Direct Mode without RS FEC figure Updated the Ethernet Hard IP Overview figure Added the Supported Applications Modes section Removed the 50GbE PAM4 w FEC application from the Supported Applications Modes table 2018 01 31 Initial release 1 Intel Stratix 10 E Tile Transceiver PHY Overview UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guid...

Page 24: ... Tile Native PHY IP core s integrated reset controller provides reset signals for the PMA Direct and PMA Direct high data rate PAM4 modes UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries Inte...

Page 25: ...lect E Tile Native PHY IP core 2 1 1 E Tile Native PHY IP Core Much like the Intel Stratix 10 L and H Tile Native PHY IP Core you have multiple options when instantiating the IP Instantiating the Native PHY IP to interface to your own IP Not instantiating the Native PHY IP as apart of your own IP and instead providing a design example which contains both the MAC IP and the Native PHY IP instances ...

Page 26: ... Direct high data rate PAM4 Based on the transceiver configuration rule that you select the Native PHY IP core guides you to configure the transceiver appropriately 5 After you configure the Native PHY IP core in the Parameter Editor click Generate HDL to generate the IP instance The top level file generated with the IP instance includes all the available ports for your configuration Use these por...

Page 27: ...ceiver interface widths and the supported data rates are pending characterization 2 2 1 General and Datapath Parameters You can customize your instance of the Native PHY IP core by specifying parameter values 2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 27 ...

Page 28: ...splays all rule violations as warnings in the message window and allows IP generation despite the violations Transceiver configuration rules PMA direct PMA direct high data rate PAM4 Gearbox 64 66 PLL Selects the protocol configuration rules for the transceiver This parameter governs the rules for the correct settings of individual parameters Certain features of the transceiver are available only ...

Page 29: ...ce switching Native PHY IP Core allows up to five clock inputs out of the possible nine for dynamic clock switching Initial TX reference clock input selection 0 This indicates the starting clock input selection used for this configuration when dynamically switching between multiple clock inputs Enable dedicated RX reference clock input On Off Option to assign dedicated reference clock for the rece...

Page 30: ...f Enables or disables the TX PMA div 66 clock option Enable TX PMA bonding On Off Enables or disables the TX PMA bonding option The parameter configures the reference clock synchronizes the master connections and so on Deskew logic requires data to be marked with a toggle bit Refer to TX PMA Bonding TX PMA clockout post divider 1 2 4 8 Specifies the post divider counter value for the tx_pma_clkout...

Page 31: ...rd pre tap pre emphasis for PAM4 For NRZ this parameter is not available Post tap 1 For PAM4 18 to 18 For NRZ 0 to 81 This is the range of the post tap pre emphasis This value is incremented by two in PAM4 mode and incremented by one in NRZ mode Use default TX PMA pre equalization settings On Off When enabled the TX PMA pre equalization settings are configured using Intel specified default setting...

Page 32: ...data rates 30 Gbps Enable RX PMA div66 clock On Off Enables or disables the RX PMA div 66 clock option Enable RX PMA full rate clock On Off Enables or disables the full rate clock of the RX PMA RX PMA clockout post divider 1 2 4 8 Specifies the post divider counter value for the rx_pma_clkout port RX PMA reference clock frequency 100 700 Selects the reference clock frequency options for the RX in ...

Page 33: ... stream This is an asynchronous output signal and is also available as part of the E Tile Native PHY register space Enable rx_pma_elecidle port On Off Enables the optional rx_pma_elecidle status port which is used for the idle 2 2 3 Core Interface Options These Native PHY IP core parameters allow you to customize the transceiver to core interface 2 Implementing the Transceiver PHY Layer in Intel S...

Page 34: ... options to customize the core interface Based on the transceiver configuration rule you select the Native PHY IP core Parameter Editor reports error or warning messages if your settings violate the protocol standard 2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 34 ...

Page 35: ...d to divide the core frequency by two so as not to exceed the maximum EMIB frequency specifications In duplex mode select this parameter for both TX and RX simultaneously 2 2 3 2 TX Clock Options Table 14 TX Clock Options Parameter Range Description Selected tx_clkout clock source Full rate half rate div66 Specifies the clock source for the tx_clkout output clock Enable tx_clkout2 port On Off Enab...

Page 36: ...ck Global Clock Specifies the type of clock network to route the clock signal to the rx_coreclkin port Dedicated Clock allows a higher maximum frequency fmax between the FPGA core and the transceiver The number of dedicated clock lines are limited 2 2 4 PMA Interface PMA interface options are related to the interface of PMA side of the bridge between the PMA and the FPGA core the FEC module and so...

Page 37: ...tes TX PMA Interface FIFO s almost full condition Enable tx_enh_pmaif_fifo _almost_empty port On Off Enables the port which indicates TX PMA Interface FIFO s almost empty condition Enable tx_enh_pmaif_fifo _overflow port On Off Enables the port which indicates TX PMA Interface FIFO s overflow condition Enable tx_enh_pmaif_fifo _underflow port On Off Enables the port which indicates TX PMA Interfac...

Page 38: ...on Select PAM4_56Gbps_LR PAM4_56Gbps_VSR NRZ_28Gbps_LR NRZ_28Gbps_VSR NRZ_10Gbps_25 15 10dB Selects preloaded PMA configuration parameters Initial Adaptation Parameters GS1 Fw_default 0 1 2 3 CTLE Low Frequency Gain Shaping 1 continued 2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 38 ...

Page 39: ...x Adaptable Fix Adaptable RF_P2 setting Fix or Adaptable options RF_P2 Min Fw_default 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 Limits RF_P2 minimum RF_P2 Max Fw_default 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 Limits RF_P2 maximum RF_P1 Fw_default 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RF_P1 setting RF_P1 Fix Adaptable Fix Adaptable RF_P1 setting Fix or Adaptable options RF_P1 Min Fw_default ...

Page 40: ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Limits CTLE HF minimum CTLE HF Max Same_as_initial_parameter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Limits CTLE HF maximum RF_P2 Same_as_initial_parameter 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 RF_P2 setting RF_P2 Fix Adaptable Fix Adaptable RF_P2 setting Fix or Adaptable options RF_P2 Min Same_as_initial_parameter 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9...

Page 41: ...nfiguration 2 2 6 Reed Solomon Forward Error Correction RS FEC Parameters The Native PHY IP Core supports RS FEC 528 514 and 544 514 You can enable this functionality by selecting the Enable RS FEC option in the Datapath Options section of the GUI Figure 22 GUI with Enable RS FEC Option Selected RS FEC merging is not supported with more than one Native PHY IP instance A Native PHY IP with an RS FE...

Page 42: ...clocking mode for the RS FEC block For some RS FEC topologies the clock selection is fixed In all other cases this control selects the TX adapter clock used to clock the RS FEC block First RS FEC Lane first_lane0 first_lane1 first_lane2 first_lane3 Selects the first RS FEC lane to be used There are four lanes in the RS FEC block When the RS FEC block is in fractured mode any of the four lanes may ...

Page 43: ...ed in the FPGA Related Information My Intel Support 2 2 6 1 Fibre Channel and CPRI Modes The core RS FEC setup is identical for 32 GFC Fibre Channel and CPRI The RS FEC options appear in the GUI after you select the Enable RSFEC option In these modes alignment codeword markers are not used and PN 5280 scrambling and descrambling are used The Number of data channels indicates how many data channels...

Page 44: ... GUI indicates an error unless you enable this option When the RS FEC aggregate mode is enabled the Native PHY IP core supports the 128 GFC mode The other RS FEC settings are the same for the aggregated 128 GFC mode and the fractured 32 GFC mode The signaling data rate for 32 GFC is 28 05 Gbps For 128 GFC the aggregate signaling data rate is 112 2 Gbps four lanes of 28 05 Gbps Figure 25 128 GFC Mo...

Page 45: ...nscoder bypass enabled The modulation scheme for this mode is PAM4 Note You must enable a special Quartus ini file to use this mode For more details contact My Intel support Related Information My Intel Support 2 2 7 Reset Parameters The Native PHY IP Core reset parameters provide reset control for the PMA interface and adapter 2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices U...

Page 46: ...ut ports to control TX and RX individually otherwise uses reset input ports to control both TX and RX Enable individual channel reset On Off When enabled you can control the channels individually Enable TX RX reset sequencing On Off When enabled the IP staggers the deassertion of the TX reset before the RX reset That is tx_reset deassertion gates rx_reset deassertion 2 2 8 Dynamic Reconfiguration ...

Page 47: ... interface On Off When enabled the Native PHY presents a single Avalon MM AVMM slave interface for dynamic reconfiguration of all channels In this configuration the upper n 1 19 address bits of the reconfiguration address bus specify the selected channel continued 2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transcei...

Page 48: ...Configuration file prefix File prefix Specifies the file prefix to use for generated configuration files when enabled Each variant of the IP should use a unique prefix for configuration files Generate SystemVerilog package file On Off When enabled The IP generates a SystemVerilog package file named Configuration file prefix _reconfig_parameters sv containing parameters defined with the attribute v...

Page 49: ...on page 165 PMA AVMM Registers on page 167 2 2 9 Port Information Table 22 Port Information Port Name Direction Width Description pll_refclk0 Input 1 bit for each channel Reference clock for the transceiver reset Input 1 bit for each channel Reset signal for the transceiver rx_serial_data Input 1 bit for each channel Positive signal for the receiver rx_serial_data_n Input 1 bit for each channel Ne...

Page 50: ...tter core interface FIFO is partially empty tx_fifo_pfull Output 1 bit for each channel Status signal indicating the transmitter core interface FIFO is partially full latency_sclk Input 1 bit for each channel Clock signal for latency measurement of the deterministic latency application rx_dl_async_pulse Output 1 bit for each channel Asynchronous output pulse signal for the receiver latency measure...

Page 51: ...te signal of the AVMM2 interface for FEC RS FEC configurations will be supported in a future release of the Intel Quartus Prime software reconfig_clk Input 1 bit Clock signal of reconfiguration interface reconfig_reset Input 1 bit Reset signal of reconfiguration interface reconfig_write Input 1 bit Write signal of reconfiguration interface reconfig_read Input 1 bit Read signal of reconfiguration i...

Page 52: ... Data 71 40 is the lower bits data Data 151 120 is the upper bits data Data 111 80 and Data 31 0 are the second data group In this group Data 31 0 is the lower bits data Data 111 80 is the upper bits data For single width transfer Data 33 and Data 113 are deskew bits deskew pulse For double width transfer Data 33 Data 73 Data 113 and Data 153 are deskew bits deskew pulse You must detect the number...

Page 53: ...ndicates the starting clock input selection used for this configuration when dynamically switching between multiple TX reference clock inputs PLL output clock frequency TBD Specifies the PLL output frequency in units of MHz PLL output 2 clock frequency TBD Specifies the PLL output frequency for output 2 in units of MHz PLL reference clock frequency Refer to the Intel Stratix 10 Device Datasheet Se...

Page 54: ... Core Parameter Editor figure Updated the General Datapath and Common PMA Options figure Added the following parameters to the PMA Interface Options table Enable tx_enh_pmaif_fifo_almost_full port Enable tx_enh_pmaif_fifo_almost_empty port Enable tx_enh_pmaif_fifo_overflow port Enable tx_enh_pmaif_fifo_underflow port Enable rx_pmaif_fifo_underflow port Enable rx_enh_pmaif_fifo_overflow port 2018 0...

Page 55: ...cy Added the following parameters to the RX PMA Options table RX PMA clockout post divider RX PMA reference clock frequency Added the Reset Parameters section Added the Dynamic Reconfiguration Parameters section Added the following ports to the Port Information table reconfig_waitrequest reconfig_readdata reconfig_writedata reconfig_address reconfig_read reconfig_write reconfig_reset reconfig_clk ...

Page 56: ...and or other countries Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel s standard warranty but reserves the right to make changes to any products and services at any time without notice Intel assumes no responsibility or liability arising out of the application or use of any information product or service described herein except ...

Page 57: ...EMIB EMIB EMIB EMIB EMIB RS FEC RS FEC PMA CH0 PMA CH1 PMA CH2 PMA CH3 PMA CH4 PMA CH5 PMA CH6 PMA CH7 PMA CH8 PMA CH9 PMA CH10 PMA CH11 FEC 528 514 or 544 514 Aggregate 100G Fractured 25G FEC 528 514 or 544 514 Aggregate 100G Fractured 25G EHIP_CORE 100G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_CORE 100G MAC P...

Page 58: ...AUI4 IEEE 802 3bs 400G Ethernet IEEE 802 3cd 50GBASE KR IEEE 802 3by 25GBASE CR 25GBASE SR CEI 25G LR CEI 28G VSR SR MR CEI 56G VSR MR LR 64GFC 32GFC Figure 32 PMA Architecture Block Diagram TX Buffer TX PMA RX PMA RX Buffer Loopback path TX Data Data Pattern Generator MUX Serializer TX EQ RX EQ Clock Recovery Sampler Data Pattern Verifier Deserializer EHIP_LANE EHIP_CORE RS FEC PMA Direct Gray En...

Page 59: ...ol interference ISI losses using an equalizer The transmitter buffer at the end of the PMA data path shapes the signal and drives the serialized data off the chip 3 1 1 1 High Speed Differential Transmitter The transmitter buffer includes the following circuitry High speed transmitter line buffer Transmitter equalizer 3 1 1 1 1 High Speed Transmitter Line Buffer The transmitter differential I O bu...

Page 60: ... a channel the high frequency components get attenuated To save power de emphasis is used instead of pre emphasis This results in a bit stream which is pre distorted by the equalizer over several bits Table 25 PMA Transmitter Programmable Parameters Parameter Mode Attenuation ATTN PAM4 NRZ Post tap1 POST PAM4 NRZ Pre tap1 PRE1 PAM4 NRZ Pre tap2 PRE2 PAM4 NRZ Pre tap3 PRE3 PAM4 NRZ Refer to the res...

Page 61: ...0 00 01 01 10 11 11 10 The transmitter also includes a precoder that you can optionally enable for both PAM4 and NRZ signals Once you turn it on it performs 1 1 D encoding on all data bits until you disable it Note More details about the gray encoder and precoder will be available in a future release of this document 3 1 1 3 Serializer The serializer converts the received parallel data into a seri...

Page 62: ...RZ patterns are different from PAM4 patterns Different specifications such as CEI OIF and IEEE 803 2 refer to quaternary PAM4 patterns differently QPRBS13 is identical to PRBSQ13 and QPRBS31 is identical to PRBSQ31 As defined in OIF Clause 16 CEI 56G VSR PAM4 Very Short Reach Interface specifications typically each cycle of PRBSQ13 is 8191 unique symbols long Each cycle is formed by gray coding an...

Page 63: ...x 1 refer to CCITT O 151 ITU T O 151 215 1 PRBS pattern This PRBS pattern 5 is based on the generator polynomial x15 x14 1 refer to CCITT O 151 ITU T O 151 223 1 PRBS pattern This PRBS pattern 6 is based on the generator polynomial x23 x18 1 refer to CCITT O 151 ITU T O 151 4 This pattern repeats every 127 bits and you can use it with a PRBS receiver to facilitate loopback testing This pattern fac...

Page 64: ...ad Write support and programming refer to PMA Register Map and PMA Attribute Codes to configure these parameters Related Information PMA Register Map on page 165 PMA Attribute Codes on page 170 3 1 2 1 1 Programmable Termination Modes Termination modes are programmable However the differential impedance values are fixed as per the Ethernet standard specifications The transceiver RX is AC coupled o...

Page 65: ...s mode tracks the temperature over time by continuously adapting new values of the RX AFE parameters This mode is a continuous and non disruptive process that is it does not impact the data traffic During a link debug process with the hard PRBS generator and verifier you cannot read out accumulated errors from the error counter unless you stop continuous adaptation Details on PMA code and value to...

Page 66: ...h min and max values 100 160 Yes 160 Related Information PMA Bring Up Flow on page 69 PMA Register Map on page 165 0x000A Receiver Tuning Controls on page 175 PMA Receiver Equalization Adaptation Usage Model on page 147 PMA Receiver Equalization Adaptation Usage Model on page 147 0x000A Receiver Tuning Controls on page 175 3 1 2 2 Clock Data Recovery CDR Block Clocking resources in the receiver en...

Page 67: ...out the LSB of the input data first Dn D2 D1 D0 Serial Data LSB Deserializer Parallel Clock Clock Serial Dn D2 D1 D0 Parallel Data 3 1 2 5 Data Pattern Verifier The data pattern verifier is used to verify the signal received at the receiver The deserialized data pattern is sent to the data pattern verifier which compares the received data pattern to the pattern it is configured to There are severa...

Page 68: ...ptation results in an optimal performance with environmental changes PMA tuning methodology optimizes link performance to reduce the bit error rate BER 3 1 3 1 Purpose of PMA Tuning You can see the value of PMA tuning by considering the following two cases Case 1 Optimum link performance measure by executing initial adaptation at static minimum and maximum temperatures Case 2 Optimum link performa...

Page 69: ...nning initial adaptation This implies that continuous adaptation is unable to maintain the performance obtained after running initial adaptation You can reduce this link performance degradation between the static temperature Case 1 and dynamic temperature Case 2 conditions by tuning the PMA AFE parameters This establishes the desired dynamic temperature performance of continuous adaptation close t...

Page 70: ...ote In DTF and STF modes initial adaptation is run in internal or serial loopback mode to calibrate the AFE parameters Note In DTF and STF modes initial adaptation is run in mission mode to calibrate AFE parameters with regards to the connected ISI channel Note Always run continuous adaptation after the following performing the steps in this order is a must to get the PMA in the correct state Inte...

Page 71: ...temperature sweep 2 If optimal performance is not achieved then sweep GS1 and GS2 first Then enter the best settings sweep the RF_B0 and RF_B1 parameters and run initial adaptation at static temperatures low and high After understanding the trend of these parameters at static temperature record the optimum value of these parameters which results in the optimum performance across the desired temper...

Page 72: ... minute Is the link performance optimum with temperature sweep Is the link performance optimum with STF across dynamic temp Sweep GS1 GS2 first record optimum values then sweep RF_B1 RF_B0 and run initial adaptation for optimum performance at static temperature You can use the PMA parameter configurations in the table below for the specified data rate and channel loss Refer to Table 30 on page 65 ...

Page 73: ...mware Default 9 GS1 1 0 2 2 GS2 1 0 2 1 RF_B0 2 3 1 1 RF_B1 8 3 1 5 CTLE LF max 2 Firmware Default 9 3 2 RF_P1_MAX 6 6 6 Firmware Default 9 RF_P2 Firmware Default 9 Firmware Default 9 0 0 RF_B0T 40 10 10 Firmware Default 9 PMA Tuning Configuration Before Running Continuous Adaptation RF_B1 Firmware Default 9 Firmware Default 9 8 Firmware Default 9 Firmware Default 9 3 1 3 4 General PMA Tuning Guid...

Page 74: ... Loopback modes Loopback modes are DFT features used to verify different blocks of the transceiver PMA Intel Stratix 10 E Tile transceivers have loopback modes to debug different blocks of the transceiver Intel Stratix 10 E Tile transceivers support the following loopback modes Internal or serial loopback Reverse parallel loopback 3 1 4 1 Internal or Serial Loopback Path The internal or serial loo...

Page 75: ... 170 3 1 4 2 Reverse Parallel Loopback Path The reverse parallel loopback path sets the transmitter buffer to transmit data fed directly from the CDR recovered data When in reverse parallel loopback mode the reference clock source of the received data stream must be the same reference clock that the transceiver channel receives 0ppm difference between the transmit and receive frequencies Additiona...

Page 76: ...ge 165 PMA Attribute Codes on page 170 3 1 5 PMA Interface The PMA interface block contains the FIFO and the gearbox Note The gearbox feature is only enabled when using RS FEC Figure 43 TX Data Flow Simplified blocks The FIFO is indicated in the red box 50 100GbE 1588 Core Interface EMIB FIFO FIFO 10 25GbE PMA Interface FIFO GB PMA Native PHY IP Core MAC Enc Scr PCS Data from four other channels R...

Page 77: ...Tile Native PHY PMA Interface Related Information Supported Applications Modes on page 21 PMA Interface on page 36 3 1 6 TX PMA Bonding TX bonding enables you to minimize skew between channels Enable bonding by selecting the Enable TX PMA bonding option in the TX PMA tab of the Native PHY IP GUI You can only bond channels within the same transceiver tile 24 channels The transceiver Native PHY IP c...

Page 78: ...essfully If it has all the bonded channels have aligned parallel data The deskew status register also provides further information for debugging if deskew is not successful cfg_tx_deskew_sts 2 0x09 4 0 not aligned or not enabled or did t receive a deskew bit 1 aligned cfg_tx_deskew_sts 1 0 0x09 3 2 00 not yet received a deskew bit 01 not aligned 10 received 1 set of aligned deskew bits 11 received...

Page 79: ...s 64B 66B encoder decoder Scrambler descrambler Block distribution block synchronization Lane reorder The PCS features are not available within the Native PHY IP core Refer to the Intel Stratix 10 E Tile Hard IP for Ethernet IP Core User Guide for details about the EHIP_LANE block Related Information E Tile Hard IP for Ethernet Intel FPGA IP User Guide 3 3 Reed Solomon Forward Error Correction RS ...

Page 80: ...ard Error Correction 3 3 1 RS FEC Modes Table 37 Example Applications for Various FEC Modes Supported RS FEC Modes RS FEC Receives Data From Example Applications Details Fractured EHIP_LANE 25GbE NRZ w FEC 528 514 You can configure all six FEC blocks per E Tile in this mode NRZ mode Four lanes within a FEC block operate independently for single lane protocols FPGA core CPRI 24G NRZ w FEC 528 514 3...

Page 81: ...s architecture blocks and the modes supported in the RS FEC blocks Note 1 This block cannot be used in combination with EHIP_CORE fractured bypass 1 3 Intel Stratix 10 E Tile Transceiver PHY Architecture UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 81 ...

Page 82: ...EMIB EMIB EMIB EMIB EMIB RS FEC RS FEC PMA CH0 PMA CH1 PMA CH2 PMA CH3 PMA CH4 PMA CH5 PMA CH6 PMA CH7 PMA CH8 PMA CH9 PMA CH10 PMA CH11 FEC 528 514 or 544 514 Aggregate 100G Fractured 25G FEC 528 514 or 544 514 Aggregate 100G Fractured 25G EHIP_CORE 100G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x2 10G 25G MAC PCS EHIP_LANE x4 10G 25G MAC PCS EHIP_CORE 100G MAC P...

Page 83: ...Configurations Implementing Various FEC Modes using the E Tile Channel Placement Tool Your implementation could vary depending on your intended application Check Table 38 on page 82 for configuration description 3 Intel Stratix 10 E Tile Transceiver PHY Architecture UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 83 ...

Page 84: ... Fractured 25G FEC 528 514 or 544 514 Aggregate 100G Fractured 25G EHIP_TOP EHIP_TOP PMA Direct PMA Direct RS FEC Legend EHIP_CORE FEC EHIP_LANE Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect FPGA Core 11 10 9 8 7 6 5 4 3 2 1 0 RS FEC RS FEC PMA CH0 PMA CH1 PMA CH2 PMA CH3 PMA CH4 PMA CH5 PMA CH6 PMA CH7 PMA CH8 PMA CH9 PMA CH10...

Page 85: ...Physical Coding Sublayer PCS Architecture section Added PMA Direct to the aggregate mode in the Example Applications for Various FEC Modes table 2018 08 08 Made the following changes Changed the equation for TX equalization for NRZ signals in the TX Equalizer section 2018 07 18 Made the following changes Added the Intel Stratix 10 E Tile Receiver PMA RX Adaptation Modes table Updated the Data Patt...

Page 86: ...ter editor provides any five reference clocks for a given design implementation You select which five based on your board layout Figure 49 IO Pad Ring Transceiver Reference Clock Input Pad Reference Clock Buffer REFCLK PAD REFCLK_N PAD_N Reference Clock Network RS1 RS2 RL1 RL2 Divide by 2 C1 C2 E Tile completes the power up configuration successfully as long as a valid reference clock frequency 12...

Page 87: ...ected transitions are not acceptable you can disable the transceiver TX output by writing the attribute code 0x0001 with data 0x0003 after power up The E Tile TX may still give some unexpected transitions between the power up phase until the attribute code 0x0001 is written After correctly configuring back the on board reference clock follow the recommended reset and device configuration steps as ...

Page 88: ...refclk_in_B REFCLK_8 Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL Divide by 2 LVPECL For details on LVPECL standard spec refer to Intel Stratix 10 Device Datasheet Related Information PMA Analog Reset on page 104 Register Map on page 165 Intel Stratix 10 Device Datasheet Intel Stratix 10 Devi...

Page 89: ...able_hysteresis enable_hyst to ref_clk 0 Recommendation Always DISABLE it as long as the reference clock characteristic meets the specification in the Intel Stratix 10 Device Datasheet Set reference clock frequency freq_in_MHz legal value set_instance_assignment name HSSI_PARAMETER refclk_divider_input_freq freq_in_MHz to ref_clk 0 Recommendation Use the same reference clock frequency number as in...

Page 90: ... RX Data TX Core FIFO XCVR Interface XCVR Interface 2 2 2 E Tile FIFO RX Core FIFO Legend TX PMA generated parallel clock line rate PMA interface width TX PMA generated parallel clock div by 2 RX PMA generated parallel clock div by 2 RX PMA generated parallel clock line rate PMA interface width 4 2 2 Single 10 Gbps PMA Direct Channel without FEC Table 41 Single 10 Gbps PMA Direct Channel Configura...

Page 91: ...rface 25 78125 Gbps 4 Enabled 32 bits 64 bits Connect half rate tx_clkout 402 83MHz to the tx_coreclkin and rx_coreclkin If you use any other source for tx_coreclkin make sure tx_coreclkin has 0 PPM difference with tx_clkout 4 2 3 1 Master Slave Configuration Option 1 All four channels use a common FEC block but FEC only uses one clock from the four available channels You can select the source cha...

Page 92: ...llel clock div by 2 RX PMA generated parallel clock line rate PMA interface width TX Core FIFO RX Core FIFO TX Core FIFO RX Core FIFO TX Core FIFO RX Core FIFO E Tile Native PHY IP TX PMA RX PMA FEC E Tile FIFO E Tile FIFO EMIB rx_coreclkin rx_clkout 402 83 MHz XCVR Interface XCVR Interface 2 2 CH1 Slave tx_clkout 402 83 MHz tx_coreclkin 25 78125 Gbps FEC TX Core FIFO RX Core FIFO 4 2 3 2 Master S...

Page 93: ...x_coreclkin2 805 66 MHz tx_coreclkin 402 83 MHz rx_clkout 402 83 MHz tx_clkout 402 83 MHz rx_coreclkin XCVR IF XCVR IF 2 2 25 78125 Gbps Native PHY PLL Mode TX Core FIFO RX Core FIFO E Tile Native PHY IP TX PMA RX PMA FEC FEC E Tile FIFO E Tile FIFO tx_coreclkin2 805 66 MHz tx_coreclkin 402 83 MHz rx_clkout 402 83 MHz tx_clkout 402 83 MHz rx_coreclkin XCVR IF XCVR IF 2 2 25 78125 Gbps Native PHY P...

Page 94: ...Data tx_coreclkin rx_coreclkin rx_clkout 402 83 MHz RX Data TX Core FIFO TX Core FIFO TX Core FIFO TX Core FIFO TX Core FIFO TX Core FIFO XCVR Interface XCVR Interface 2 2 CH3 E Tile Native PHY IP TX PMA 25 78125 Gbps RX PMA E Tile FIFO E Tile FIFO EMIB tx_clkout 402 83 MHz TX Data tx_coreclkin rx_coreclkin rx_clkout 402 83 MHz RX Data XCVR Interface XCVR Interface 2 2 CH2 E Tile Native PHY IP TX ...

Page 95: ... Gbps each where all four lanes must use the same FEC block FEC is clocked by one of the four channels and you can configure this in the Native PHY IP core Parameter Editor There is an inherent dependency between channels in this configuration However for applications like 100 GbE dependency is acceptable and sometimes required For each of the four channels with Core Interface FIFOs in Phase Compe...

Page 96: ...2 CH0 Master tx_clkout 402 83 MHz tx_coreclkin 25 78125 Gbps FEC Legend TX PMA generated parallel clock line rate PMA interface width TX PMA generated parallel clock div by 2 RX PMA generated parallel clock div by 2 RX PMA generated parallel clock line rate PMA interface width TX Core FIFO RX Core FIFO TX Core FIFO RX Core FIFO TX Core FIFO RX Core FIFO E Tile Native PHY IP TX PMA RX PMA FEC E Til...

Page 97: ...8 10 08 Made the following changes Updated the Clock Sharing 25G Ethernet 24G CPRI figure Updated the Clock Sharing 25G Ethernet 24G CPRI PMA Direct figure Added Use Cases and all subsections Removed the Clocking Sharing Across Multiple IPs section Added the E Tile Channel Placement for a Single 25 Gbps PMA Direct Channel with FEC Within a Single FEC Block figure Changed the QSF assignment for all...

Page 98: ...n is complete Figure 57 Enabling PMA Calibration Disable the PMA using attribute code 0x0001 Update the PMA settings using associated PMA attribute codes Enable PMA using PMA attribute code 0x0001 Wait for tx_pma_ready and rx_pma_ready ports to assert Request PMA calibration once the PMA is enabled using PMA attribute code 0x0011 UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reser...

Page 99: ...led 2018 07 18 Made the following changes Added instructions to PMA Calibration When dynamically reconfiguring the PMA to a different datarate you need to recalibrate the PMA The PMA calibration is run when the PMA is enabled so you first disable the PMA Added the Wait for tx_pma_ready and rx_pma_ready ports to assert block to the Enabling PMA Calibration figure 2018 05 15 Made the following chang...

Page 100: ...g the digital reset controller in the Native PHY IP There are special reset procedures to follow if the E Tile Native PHY IP core is configured with the RS FEC enabled Table 44 Reset Requirements when RS FEC is Enabled Number of Channels Enable RS FEC Enable Datapath and Interface Aggregate Mode Reset Controller 1 to 24 No No N A Manual or automatic mode 1 to 3 Yes No N A Bypassed 1 to 3 Yes Yes N...

Page 101: ...r Use the steps below when both digital and analog resets are needed Changing the data rate is an example of when both digital and analog resets are needed 1 Assert the digital reset controller See High Level Specification for the ports and sequence 2 Wait for the Native PHY s tx_ready rx_ready outputs to deassert 3 Assert the PMA reset on the AVMM reconfiguration bus using PMA attribute code 0x00...

Page 102: ...se steps 1 Select Assignment Settings 2 Click Device Board in the top right corner 3 Select Device and Pin Options 4 Select 25 MHz OSC_CLK_1 pin 100 MHz OSC_CLK_1 pin or 125 MHz OSC_CLK_1 pin as the Configuration clock source Figure 58 Device and Pin Options 6 3 Reset Block Architecture The Native PHY IP core s digital reset controller block interacts with a master and local transceiver reset sequ...

Page 103: ...ust be followed Note The master and local TRS IP is an inferred block and is not visible in the RTL You have no control over this block Table 45 Reset Signals Required for E Tile Reset Transceiver Reset Category tx_reset TX EMIB reset EMIB Reset TX PMAIF reset Transceiver Interface Reset RS FEC reset RS FEC Reset TX RS FEC reset General RS FEC reset and includes the TX and RX datapath rx_reset RX ...

Page 104: ...s adaptation is running unplugging the optical link then plugging it back in The PMA is stuck in an unknown state there is a high BER reported with no CDR lock initial adaptation does not help in recovery Powering up Initial adaptation does not help bring up the device in a good state Correcting a loose cable connection and bring up a link Initial adaptation does not help bring up the device in a ...

Page 105: ...t the Local TRS sends the reset event to the transceiver channels If required the Local TRS sequences the actual reset signals that go to the channels and adds extra delays to the reset assertion or deassertion After the Local TRS is done with the reset it drops the reset request then the Master TRS moves to the next Local TRS request There are two variants of Local TRS TX LTRS and RX LTRS The TX ...

Page 106: ...configure the RS FEC EMIB PMAIF you must assert tx_reset until the RS FEC EMIB PMAIF registers are written tx_ready Use the AVMM bus to reset reconfigure the PMA or reconfigure RS FEC EMIB PMAIF optional Figure 63 RX Reset Sequence in Automatic Mode After Power Up rx_reset 1 rx_pma_ready if PMA is reset configured rx_ready Use the AVMM bus to reset reconfigure the PMA or reconfigure RS FEC EMIB PM...

Page 107: ...PMA is ready This must be asserted before asserting or deasserting any RX resets rx_is_lockedtodata Output Output from the PMA indicating the CDR has locked to the incoming serial data tx_reset_req Input Request to Master TRS to schedule TX reset tx_reset_ack Output Valid window to assert or deassert tx_aib_reset tx_pmaif_reset tx_rsfec_reset rsfec_reset rsfec_reset Input Reset all RS FEC logic tx...

Page 108: ...el before resetting the RX on that channel You must ensure that the tx_pma_ready output is asserted before asserting the tx_reset_req You must ensure that the rx_pma_ready output is asserted before asserting the rx_reset_req You must monitor rx_is_lockedtodata After rx_lockedtodata stays high for 180 µs you may deassert the RX digital resets The following use model is supported 1 You assert multip...

Page 109: ...set Timing Model During the timing window when the reset_ack output is high reset the blocks in sequence The numbers refer to the steps above t t t t reset_req 0 reset_req 1 reset_req 2 reset_req 3 reset_ack 0 reset_ack 1 reset_ack 2 reset_ack 3 t 200 ns 1 2 4 5 6 Figure 66 on page 109 and Figure 67 on page 110 below show how to assert TX and RX reset Figure 66 RX Reset Assertion Timing Waveform r...

Page 110: ...ert TX and RX reset Figure 68 RX Reset Deassertion Timing Waveform rx_pma_ready rx_reset_req 1 rx_reset_ack rx_aib_reset rx_transfer_ready rx_is_lockedtodata rx_pmaif_reset rx_rsfec_reset Note 1 If you have enabled the RS FEC block you must assert rx_reset_req after the tx_transfer_ready output is asserted Min 180 µs Min 100 ns 6 Resetting Transceiver Channels UG 20056 2019 02 04 Intel Stratix 10 ...

Page 111: ...71 on page 112 below for details The RS FEC block automatically locks onto the FEC symbols and you do not need to reset the RS FEC block through the rsfec_reset tx_rsfec_reset or rx_rsfec_reset signals Figure 70 RX PMA Reconfiguration with Reset Controller in Manual Mode Timing Waveform rx_pma_ready rx_reset_req 1 rx_reset_ack rx_aib_reset rx_pmaif_reset rx_rsfec_reset AVMM rx_transfer_ready Reset...

Page 112: ...IP cores with the following configurations Instance A with one transceiver channel with RS FEC disabled and the reset controller in automatic mode Instance B with four transceiver channels with RS FEC enabled in aggregate mode and the reset controller in manual mode Instance C with two transceiver channels with RS FEC enabled in fractured mode and the reset controller bypassed If you want to reset...

Page 113: ...t from the PMA indicating the TX PMA is ready This must be asserted before asserting or deasserting any TX resets Figure 72 Reset Controller Bypass Ports E Tile Native PHY IP Reset Controller RS FEC EMIB PMA Interface Master TRS Request Acknowledgement TX RX PMA rsfec_reset tx_rsfec_reset rx_rsfec_reset tx_aib_reset rx_aib_reset tx_transfer_ready rx_transfer_ready tx_pma_ready rx_pma_ready tx_pmai...

Page 114: ...c_reset tx_rsfec_reset tx_pmaif_reset AVMM tx_transfer_ready Reset and reconfigure PMA using PMA attribute codes Min 100 ns Min 100 ns Min 100 ns Min 100 ns 6 6 Intel Quartus Prime Instantiated Transceiver Reset Sequencer Intel Quartus Prime auto infers the Master TRS during synthesis and auto connects the Master TRS to the Local TRS using the debug fabric master end point to slave end point auto ...

Page 115: ...debugging the RTL Any issue with the instantiation and connectivity needs to be fixed in Synthesis instead of in the design 6 7 Block Diagrams Figure 75 General Block Diagram for Reset Controller when Use Separate TX RX Reset Per Channel is Turned ON and Enable Individual TX and RX Reset is Turned OFF E Tile Native PHY IP Reset Controller N Reset Controller 0 rx_ready 0 tx_ready 0 reset 0 rx_ready...

Page 116: ... tx_ready 0 rx_reset 0 tx_reset 0 rx_ready N tx_ready N rx_reset N tx_reset N Figure 77 Reset Controller when Use Separate TX RX Reset Per Channel is Turned OFF and Enable Individual TX and RX Reset is Turned OFF E Tile Native PHY IP Reset Controller rx_ready N 0 tx_ready N 0 reset 0 reset N 1 6 Resetting Transceiver Channels UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide S...

Page 117: ...180 μs before deasserting reset You can set this parameter for additional filtering 6 8 2 HDL Ports Interfaces Table 50 HDL Ports Interfaces when the Reset Controller is in Automatic Mode Port Name Direction Width Description reset Input Number of channels Resets TX and RX when asserted Visible when Enable individual TX and RX resets is disabled When the Native PHY is configured in PAM4 high datar...

Page 118: ...nel is Turned OFF and Enable Individual TX and RX Reset is Turned OFF figure Added the Enable TX RX reset sequencing parameter to the Reset Parameters table 2018 07 18 Made the following changes Updated the RX Reset Deassertion Timing Waveform sequence Moved AVMM to between first falling edge of rx_reset_req and rx_pma_ready rising edge in RX PMA Reconfiguration with Reset Controller in Manual Mod...

Page 119: ...reconfiguration streamer Altera Debug Master Endpoint ADME Optional reconfiguration logic Also see Unsupported Features The RS FEC AVMM interface allows you to reconfigure the RS FEC block and monitor status Further information about how RS FEC can be changed from one mode to another will be included in a future user guide release Related Information Unsupported Features on page 121 UG 20056 2019 ...

Page 120: ...nel Communication with the channel reconfiguration interface requires an AVMM master Because each channel has its own dedicated AVMM interface you can dynamically reconfigure channels either concurrently or sequentially depending on how the AVMM master is connected to the AVMM reconfiguration interface Figure 78 Reconfiguration Interface in Intel Stratix 10 Transceiver IP Cores Ch0 AVMM Reconfigur...

Page 121: ...config_read reconfig_writedata reconfig_address reconfig_readdata reconfig_waitrequest 7 3 Unsupported Features Dynamic reconfiguration between the following modes is not supported by the Transceiver Native PHY IP core PMA direct high data rate PAM4 PMA direct bonded mode Non RS FEC to RS FEC reconfiguration 7 4 Reading from the Dynamic Reconfiguration Interface Reading from the reconfiguration in...

Page 122: ...n constant 4 The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest 5 The master samples reconfig_waitrequest and reconfig_readdata completing the transfer 0x00119 Valid readdata 17 reconfig_clk cycles 7 5 Writing to the Dynamic Reconfiguration Interface Writing to the reconfiguration interface of the Transceiver Native PHY IP core changes the data value at a specific addres...

Page 123: ... paths for all configurations based on initial and target profiles You can also generate full reconfiguration files or reduced configuration files that contain only the attributes that differ between the multiple configured profiles You can create up to eight reconfiguration profiles Profile 0 to Profile 7 at a time for each Native PHY instance The configuration files generated by Native PHY IP al...

Page 124: ...parameters_CFG0 localparam ram_depth 21 function 34 0 get_ram_data input integer index automatic reg 0 20 34 0 ram_data 35 h0380706 34 16 DPRIO address 0x038 15 8 bit mask 0x07 2 2 hssi_xcvr_cfg_rb_cont_cal dcc_cont_cal_en 1 h1 1 1 hssi_xcvr_cfg_rb_dcc_en dcc_mast_en 1 h1 0 0 hssi_xcvr_cfg_rb_dcc_byp dcc_byp_dis 1 h0 35 h03C0202 34 16 DPRIO address 0x03C 15 8 bit mask 0x02 1 1 hssi_xcvr_cfg_dcc_cs...

Page 125: ...on MM transactions to access channel configuration registers in the transceiver When you enable the embedded streamer the Native PHY IP cores embed HDL code for reconfiguration profile storage and reconfiguration control logic in the IP files If the new profile requires changing PMA attributes that can only be performed when the PMA is disabled you need to do the following 1 Assert digital reset 2...

Page 126: ...figuration streamer has the highest priority followed by the reconfiguration interface followed by the ADME When two feature blocks are trying to access the same transceiver channel on the same clock cycle the feature block with the highest priority is given access The only exception is when a lower priority feature block is in the middle of a read write operation and a higher priority feature blo...

Page 127: ...ode 0x0001 Update PMA settings using PMA register read write codes listed in Chapter 9 2 Set the PMA to internal or serial loopback using PMA register read write code 0x0008 Enable the PMA using PMA register read write code 0x0001 Enable Initial RX Equalizer Adaptation Mode using PMA register read write code 0x000A Disable PMA internal or serial loopback using PMA register read write code 0x0008 R...

Page 128: ... indicated in the manual reset section of the reset chapter Enable the PMA using PMA attribute code 0x0001 Enable the Initial RX Equalizer Adaptation Mode using PMA attribute code 0x000A Wait for tx rx_reset_ack asserts Assert tx rx_reset_req Wait for the tx rx_pma_ready to assert Example Change the PMA data rate from 25 Gbps to 20 Gbps Update PMA settings that can be changed while the PMA is runn...

Page 129: ...ynamic reconfiguration can be performed on logical operations such as switching between multiple reference clocks In these cases configuration files alone cannot be used Configuration files are generated during IP generation and do not contain information on the placement of reference clocks To perform dynamic reconfiguration on logical operations you must use lookup registers that contain informa...

Page 130: ...l controller is clocked by the reference clock so changing the reference clock can cause a glitch 6 Set 0x91 to 0x01 if you want to Go to the initial PMA configuration when the embedded reconfiguration streamer is not used Go to the last selected profile when the embedded reconfiguration streamer is used 0x91 0 automatically clears once the PMA is loaded with the correct settings 7 If you want to ...

Page 131: ...ary encoded to specify the four channels For example 2 b01 in reconfig_address 20 19 specifies logical channel 1 The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled Figure 85 Reconfiguration Interface Ports with Shared Native PHY Reconfiguration Interface Native PHY IP Core reconfig_c...

Page 132: ...ration address bus of logical channel 0 reconfig_address_ch1 18 0 correspond to the reconfiguration address bus of logical channel 1 reconfig_address_ch2 18 0 corresponds to the reconfiguration address bus of logical channel 2 and reconfig_address_ch3 18 0 correspond to the reconfiguration address bus of logical channel 3 The following figure shows the signals available when the Native PHY is conf...

Page 133: ...fig_waitrequest_ch0 Output reconfig_clk_ch A one bit signal for each channel that indicates that the AVMM interface is busy Keep the AVMM command asserted until the interface is ready to proceed with the read write transfer Table 55 AVMM Interface Parameters The following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY parameter editors Parameter Value Des...

Page 134: ...onfiguration data values for all reconfiguration addresses Disabled by default Enable multiple reconfiguration profiles On Off Use the Parameter Editor to store multiple configurations The parameter settings for each profile are tabulated in the Parameter Editor Enable embedded reconfiguration streamer On Off Embeds the reconfiguration streamer into the Native PHY IP core and automates the dynamic...

Page 135: ...rough the system console You can enable ADME using the Enable Altera Debug Master Endpoint option available under the Dynamic Reconfiguration tab in the Native PHY IP cores When using ADME the Intel Quartus Prime software inserts the debug interconnect fabric to connect with USB JTAG or other net hosts Select the Share Reconfiguration Interface parameter when the Native PHY IP instance has more th...

Page 136: ... Recommendations Intel recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP core if any of the modified or target configurations involve changes to RS FEC settings Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as TX VOD swing or refclk switching When performing a dynamic reconfiguration...

Page 137: ...built in logic to load one of them to all transceiver channels in the instance at run time SeeLoading IP Configuration Settings Process for more details and Configuring a PMA Parameter Using Native PHY IP for an example Related Information Loading IP Configuration Settings on page 137 PMA Tuning on page 68 Loading IP Configuration Settings Process on page 137 Configuring a PMA Parameter Tunable by...

Page 138: ...18 07 18 Made the following changes Added reconfiguring the PMA between NRZ and PAM4 non high datarate modes as a feature to the Dynamic Reconfiguration Feature Support table Added Multiple Reconfiguration Profiles Updated Reconfiguration Files with entirely new information Added Embedded Reconfiguration Streamer Updated the steps in the Switching Reference Clocks section 2018 05 15 Made the follo...

Page 139: ...ction Removed reference to the PMA register read write sequencer for this release pending testing in the Changing Analog PMA Settings section Updated the address writedata and readdata bus widths in the Ports and Parameters and ADME sections 2018 01 31 Initial release 7 Dynamic Reconfiguration UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 139 ...

Page 140: ...on Flow 1 Assert tx_reset rx_reset 2 Wait for the tx_ready rx_ready to deassert 3 Disable the PMA by using PMA attribute code 0x0001 a Write 0x84 7 0 0x00 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x01 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reserved Intel the Intel logo A...

Page 141: ...rite 0x85 7 0 0x80 bit 7 applies the update to both TX RX c Write 0x86 7 0 0x05 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value 9 Change serialization deserialization factor to 40 bits wide by using PMA attribute code 0x0014 a Write 0x84 7 0 0x33 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x14 d...

Page 142: ...e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value 13 Enable initial coarse adaptive equalization by using PMA attribute code 0x000A a Write 0x84 7 0 0x01 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x0A d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8...

Page 143: ...ributes for PRBS Through AVMM Registers 0x00 0x02 0x01 0x25 0x87 0x86 0x85 0x84 7 6 5 4 3 2 1 0 Load RX PRBSGEN Load TX PRBSGEN 7 6 5 4 3 2 1 0 Stop on error Reserved Auto seed correct Reseed on Error Reserved PRBS Pattern 2 0 3 b000 PRBS7 3 b001 PRBS9 3 b010 PRBS11 3 b011 PRBS15 3 b100 PRBS23 3 b101 PRBS31 3 b110 PRBS13 3 b111 User PMA code address PMA code value 0x90 7 0 0 0 7 7 0x8B 0x8A Reques...

Page 144: ...ted configuration Wait some time and re issue the request 0x02 Success For example to use the PRBS31 generator and checker do the following steps 1 Set TX PRBS31 a Write 0x84 7 0 0x25 b Write 0x85 7 0 0x01 c Write 0x86 7 0 0x02 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value 2 Set RX PRBS31 ...

Page 145: ...error counters a Write 0x84 7 0 0x00 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x17 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value 7 Wait for the 32 bits wide error counter to be accumulated 8 Set the error count to be read out a Write 0x84 7 0 0x03 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x18 ...

Page 146: ...sents bits 23 16 of the error counter j Read 0x89 7 0 This represents bits 31 24 of the error counter Note During PMA performance verification testing with continuous adaptation running in background error bits cannot be accumulated to calculate BER because the Hard PRBS error counter is in a busy state You can read errors during continuous adaptation by implementing a soft PRBS generator and veri...

Page 147: ...c Write 0x86 7 0 0x1B d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value 2 Set Error Injection for injecting burst of 10 bit errors a Write 0x84 7 0 0x0A b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x1B d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it cha...

Page 148: ...PMA 0 Status of request made to PMA 7 7 0 0 0 7 7 Initial Adaptation The procedure is as follows 1 Configure PMA attribute code 0x2B as following to set the RX termination to floating a Write 0x84 7 0 0x02 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x2B d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 ...

Page 149: ...ad 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 b1 to clear the 0x8A 7 value i Read 0x88 0 5 Repeat Step 4 until 0x88 0 goes from 1 to 0 Continuous Adaptation 1 Configure PMA attribute code 0x0A as following to enable continuous adaptation a Write 0x84 7 0 0x06 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x0A d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It sh...

Page 150: ...0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 to clear the 0x8A 7 flag 3 Load pattern 9 0 a Write 0x84 7 0 0x33 b Write 0x85 7 0 0x03 c Write 0x86 7 0 0x19 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 to clear the 0x8A 7 flag 4 Load pattern 19 1...

Page 151: ... to 0 h Write 0x8A 7 to 1 to clear the 0x8A 7 flag 7 Load pattern 49 40 a Write 0x84 7 0 0x33 b Write 0x85 7 0 0x03 c Write 0x86 7 0 0x19 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 to clear the 0x8A 7 flag 8 Load pattern 59 50 a Write 0x84 7 0 0xCC b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x19 d Write 0x87 7 0 0x00 e...

Page 152: ...0x8A 7 flag 11 Load the TX PRBS generator with your pattern a Write 0x84 7 0 0x27 b Write 0x85 7 0 0x01 c Write 0x86 7 0 0x02 d Write 0x87 7 0 0x00 e Write 0x90 0 1 b1 f Read 0x8A 7 It should be 1 g Read 0x8B 0 until it changes to 0 h Write 0x8A 7 to 1 to clear the 0x8A 7 flag 12 Enable the PMA TX output a Write 0x84 7 0 0x07 b Write 0x85 7 0 0x00 c Write 0x86 7 0 0x01 d Write 0x87 7 0 0x00 e Writ...

Page 153: ...ing the post_tap emphasis of the TX Equalizer with PMA attribute values of 2 decimal and 0x02 hexadecimal or 2 decimal and 0xFE hexadecimal and PMA attribute code of 0x15 1 Write 0x84 7 0 0x02 for 2 decimal or write 0x84 7 0 0xFE for 2 decimal 2 Write 0x85 7 0 0x80 3 Write 0x86 7 0 0x15 4 Write 0x87 7 0 0x00 5 Write 0x90 0 1 b1 6 Read 0x8A 7 It should be 1 7 Read 0x8B 0 until it changes to 0 8 Wri...

Page 154: ... the PMA Driver This procedure inverts the TX polarity 1 Write 0x84 7 0 0x01 2 Write 0x85 7 0 0x03 3 Write 0x86 7 0 0x13 4 Write 0x87 7 0 0x00 5 Write 0x90 0 1 b1 6 Read 0x8A 7 It should be 1 7 Read 0x8B 0 until it changes to 0 8 Write 0x8A 7 to 1 to clear the 0x8A 7 flag 8 10 Inverting RX Polarity for the PMA Driver This procedure inverts the RX polarity 1 Write 0x84 7 0 0x10 2 Write 0x85 7 0 0x0...

Page 155: ...ck A 0xD04 0xD03 RF_B1 RF_B0 CTLE BLOCK A Parameter Value 6 5 4 3 2 1 0 Block A 0x109 CTLE 0x108 0 6 5 4 3 2 1 0 0 0 RF_B1 RF_B0 RF_P0 RF_P1 RF_P2 0 GS1 GS2 0 HF LF Example Set GS1 to 0x01 Attr Code Attr Value 0x2c 0x904 Attr Code Attr Value 0x6c 0x01 Attr Code Attr Value 0xec 0x15 Attr Code Attr Value 0x2c 0x108 0x6c 0x20 Select the parameter Write value to parameter Load value to parameter Fix v...

Page 156: ...attribute value 0x20 26 Write 0x84 7 0 0x08 27 Write 0x85 7 0 0x01 28 Write 0x86 7 0 0x2C 29 Write 0x87 7 0 0x00 30 Write 0x90 0 1 b1 31 Read 0x8A 7 It should be 1 32 Read 0x8B 0 until it changes to 0 33 Write 0x8A 7 to 1 to clear the 0x8A 7 flag 34 Write 0x84 7 0 0x20 35 Write 0x85 7 0 0x00 36 Write 0x86 7 0 0x6c 37 Write 0x87 7 0 0x00 38 Write 0x90 0 1 b1 39 Read 0x8A 7 It should be 1 40 Read 0x...

Page 157: ...e PHY instance Program the device with the resulting sof Open the System Console and link the design Transceiver PMA Bring Up is user triggered and requires configuring a few registers 3 4 5 The transceiver PMA is set to the selected test configuration Note 1 Refer to PMA Adaptation for PMA Adaptation Tab details 2 Refer the PMA Adaptation Options table for details 3 Refer to PMA Bring Up Flow 4 R...

Page 158: ...MA Bring Up Flow To get optimal performance from the PMA across dynamic temperature conditions PMA parameter tuning is required before initiating receiver initial adaptation and receiver continuous adaptation What follows is the Native PHY IP GUI configuration flow 8 Dynamic Reconfiguration Examples UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 158 ...

Page 159: ...ters to the required settings before initiating initial adaptation and continuous adaptation The PMA configurations listed have been validated across PVT as per IEEE 802 3bs bj specifications If you have a different test setup you must tune some of the parameters to achieve the optimal performance across the PVT 4 Initial adaptation and continuous adaptation PMA parameter options are 8 Dynamic Rec...

Page 160: ...d adaptable 2 Continuous Adaptation parameter values options are same_as_initial_parameter and all legal values Multi PMA Configuration Support One native PHY supports up to eight different PMA configurations You can choose one PMA configuration and load it for editing The table shows the settings in each PMA configuration which provides an overview of all PMA configurations PMA Adaptation setting...

Page 161: ...Load your PMA configuration and apply it to all channels Figure 96 Enable Soft IP GUI To enable the soft IP turn on Enable dynamic reconfiguration and Enable control and status registers 8 Dynamic Reconfiguration Examples UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 161 ...

Page 162: ...r of chnls Transceiver in Required Configuration Y N In the above flow the transceiver reset is required only for non Hard PRBS designs meaning that the data is coming to the transceiver tile from the FPGA core Refer to Loading a PMA Configuration for more details Related Information PMA Adaptation on page 37 PMA Bring Up Flow on page 69 PMA Analog Reset on page 104 8 Dynamic Reconfiguration Examp...

Page 163: ...tial adaptation continuous adaptation or both are run loopback mode is set PRBS is set etc 9 Write 0x200 0xd2 This is running initial adaptation would run continuous adaptation if selected above loads the PMA configuration to the registers for this channel and again ensures PRBS31 is used for this command 10 Write 0x201 0x02 This sets internal or serial loopback again as part of this command 11 Wr...

Page 164: ...and Configuring RX Polarity for the PMA Driver Switched the order of all write commands and added the step to Write 0x8A 7 to 1 to clear the 0x8A 7 flag in User Defined Pattern Example Added Configuring the Attenuation Value VOD Added Configuring the Post Emphasis Value Added Configuring pretap1 Values Changed the names of the adaptive equalization modes in the PMA Receiver Equalization Adaptation...

Page 165: ...annel ID for each channel in the instance Duplex 0x40012 1 0 read only Shows transceiver mode 2 b11 Duplex Refer to PMA Attribute Codes for details about the PMA attribute codes and values Related Information PMA Attribute Codes on page 170 UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words a...

Page 166: ...ce Reset Override 4 read write Override selects between soft AVMM and reset controller Set to 0 for the reset controller to set the reset and 1 for AVMM register 0x400E2 0 to set the value RX AIB Reset Override 5 read write Override selects between soft AVMM and reset controller Set to 0 for the reset controller to set the reset and 1 for AVMM register 0x400E2 1 to set the value TX PMA Interface R...

Page 167: ...0 TX datapath clock enable 1 Transmit full clock out PMA Clock enable 4 2 Transmit data input select 5 Transmit full clock out clk_tx_adapt select 6 Transmit clock datapath select 7 Transmit adaptation order select Determines how 64 bits are sent to 32 bit transceiver channel 0x5 1 0 Transmit multi lane data select 2 TX Gearbox clock enable 3 TX datapath clock enable 4 TX PCS div2 clock input enab...

Page 168: ... bit 01 not aligned 10 received 1 set of aligned deskew bits 11 received 16 sets of aligned deskew bits 4 TX deskew alignment status 0 not aligned or not enabled or didn t receive a deskew bit 1 aligned 5 RX FIFO bit 67 select 0xA 2 0 Transmit deskew enable using one hot encoding 5 Dynamic rx_bitslip enable 0x10 4 0 Transceiver interface RX FIFO empty threshold 7 6 Transceiver interface RX FIFO al...

Page 169: ...en the user_reset is active after FPGA initialization 0x24 2 0 Transmit output value 66 64 when the user_reset is active after FPGA initialization 0x34 1 0 Serialization factor for rx_bit_counter 7 4 The value at which rx_bit_counter should reset to 0 Set to 5280 32 for RS FEC 0x35 7 0 The value at which rx_bit_counter should reset to 0 Set to 5280 32 for RS FEC 0x36 0 The value at which rx_bit_co...

Page 170: ...3 in the Native PHY IP core 0x200 7 0 Set the address to 0x00 to reset the PMA when changing the PMA s reference clock 0x201 7 0 Set the address to 0x00 to reset the PMA when changing the PMA s reference clock 0x202 7 0 Set the address to 0x00 to reset the PMA when changing the PMA s reference clock 0x203 7 0 Set the address to 0x81 to reset the PMA when changing the PMA s reference clock 0x204 0 ...

Page 171: ...ode 0x0002 Description Controls the PRBS settings for the PMA 0x84 2 0 3 b000 to set to PRBS7 0x84 2 0 3 b001 to set to PRBS9 0x84 2 0 3 b010 to set to PRBS11 0x84 2 0 3 b011 to set to PRBS15 0x84 2 0 3 b100 to set to PRBS23 0x84 2 0 3 b101 to set to PRBS31 0x84 2 0 3 b111 to set to user defined pattern Setting it to user defined pattern disables the PRBS 0x84 3 1 b0 0x84 4 Reseed on error 0x84 5 ...

Page 172: ...3 b000 to select rx_data as source data for comparison 0x84 6 4 3 b010 to select RX pattern generator data as source data for comparison 0x84 6 4 3 b011 to select tx_data as source data for comparison 0x84 6 4 3 b100 to select tx_prbs as source data for comparison 0x84 6 4 3 b110 to select 20 h00000 as source data for comparison 0x84 6 4 3 b111 to select 20 hFFFFF as source data for comparison 0x8...

Page 173: ...te 0x85 2 0 3 b010 to set the TX running at quarter rate 0x85 2 0 3 b011 to set the TX running at one eighth rate 0x85 3 1 b0 0x85 4 1 b1 to configure the PMA channel as a slave channel when multiple channels are bonded 0x85 5 1 b0 0x85 6 1 b0 to select refclk_in_a as the TX reference clock 0x85 6 1 b1 to select refclk_in_b as the TX reference clock 0x85 7 1 b1 to apply settings to both TX and RX ...

Page 174: ... Running While Updating PMA Attribute No Return Value 0x89 7 0 0x88 7 0 0x00FF Invalid configuration 0x0006 Success Related Information Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 on page 187 9 2 6 0x0008 Internal or Serial Loopback and Reverse Parallel Loopback Control Attribute Code 0x0008 Description Controls turning on off internal or serial loopback or reverse paralle...

Page 175: ...uning and controls how some tuning knobs are used 0x84 3 0 4 b0001 Run initial adaptive equalization 0x84 3 0 4 b0010 Freeze continuous adaptive equalization to allow the error counter to be read out when the PRBS generator verifier is enabled the Freeze adaptation mode 0x84 3 0 4 b0110 Run continuous adaptive equalization 0x84 7 4 0x0 0x85 7 0 0x00 PMA Can Be Running While Updating PMA Attribute ...

Page 176: ...ay code in PAM4 mode 0x84 2 1 b1 to enable TX Precode 1 1 D in PAM4 mode 0x84 3 1 b0 for even bits to be mapped to PAM4 LSB 0x84 3 1 b1 for even bits to be mapped to PAM4 MSB 0x84 4 1 b1 to invert RX polarity 0x84 5 1 b1 to enable RX Gray code in PAM4 mode 0x84 6 1 b1 to enable RX Precode 1 1 D in PAM4 mode 0x84 7 1 b0 for RX even bits to be mapped to PAM4 LSB 0x84 7 1 b1 for RX even bits to be ma...

Page 177: ... 1 b1 to set TX in PAM4 mode 0x84 3 1 b0 to set TX in NRZ mode 0x84 6 4 3 b001 to set RX in 20 bit width NRZ only 0x84 6 4 3 b011 to set RX in 40 bit width NRZ or PAM4 0x84 6 4 3 b100 to set RX in 16 bit width NRZ only 0x84 6 4 3 b101 to set RX in 32 bit width NRZ or PAM4 0x84 6 4 3 b110 to set RX in 64 bit width PAM4 only 0x84 7 1 b1 to set RX in PAM4 mode 0x84 7 1 b0 to set RX in NRZ mode 0x85 7...

Page 178: ... 7 4 4 b0011 to set read the TX pre emphasis tap 3 value 0x85 7 4 4 b0100 to set read the main tap value 0x85 7 4 4 b1000 to set read the Post emphasis tap 1 value 0x85 7 4 4 b1100 to set read the TX pre emphasis tap 2 value PMA Can Be Running While Updating PMA Attribute Yes Return Value 0x89 7 0 0x88 7 0 If 0x85 0 is 1 b1 EQ value If 0x85 0 is 1 b0 0x0015 if success 0x0000 if failed to apply sin...

Page 179: ...t a time starting from the LSB by asserting PMA attribute code 0x1A assert the PMA attribute code two times 0x85 7 0 0x84 7 0 0x0003 Select 32b wide error counter to be read 16b at a time starting from the LSB by asserting PMA attribute code 0x1A assert the PMA attribute code two times 0x85 7 0 0x84 7 0 0x0004 Select 80b wide recovered RX data to be read 10b at a time starting from the LSB by asse...

Page 180: ...te Yes Return Value 0x89 7 0 0x88 7 0 Varies 9 2 16 0x001B TX Error Injection Signal Attribute Code 0x001B Description Switches the TX error injection signal on or off for the number of times requested 0x85 7 0 0x84 7 0 Number of errors to inject PMA Can Be Running While Updating PMA Attribute Yes Return Value 0x89 7 0 0x88 7 0 0x001B 9 2 17 0x001C Incoming RX Data Capture Attribute Code 0x001C 9 ...

Page 181: ...8 7 0 0x88 4 1 b1 if error occurred 0x88 4 1 b0 if no error 9 2 19 0x002B RX Termination and TX Driver Tri state Behavior Attribute Code 0x002B Description Sets RX termination and TX driver tri state behavior 0x84 0 1 b0 RX termination to ground 0x84 0 1 b1 RX termination to VCC 0x84 1 1 b0 Active termination to ground VCC based on 0x84 0 0x84 1 1 b1 Termination undriven floating 0x84 3 2 2 h0 0x8...

Page 182: ...0x88 7 0 0x88 0 1 b1 if initial coarse adaptive equalization in progress 0x88 4 1 b1 if initial coarse adaptive equalization is enabled 0x88 5 1 b1 if fine adaptive equalization is enabled 0x88 6 1 b1 if continuous adaptive equalization is enabled 0x88 7 1 b1 if input offset correction finished 0x89 1 1 b1 if electrical idle is detected during initial coarse adaptive equalization 9 2 21 Reading an...

Page 183: ... Analog Parameters To write a new value to an analog parameter for the RX adaptation to use as the starting value 1 Use attribute code 0x002C to read the parameter value 2 Use attribute code 0x006C to enter the new value on 0x85 7 0 0x84 7 0 as a two s complement number The analog parameter written is determined by the last previous analog parameter read Registers 0x89 7 0 0x88 7 0 return 0x002C t...

Page 184: ...to fix GS1 or 1 b0 to allow adaptation to set GS1 0x84 7 6 2 b00 0x85 7 0 8 h00 The return value on registers 0x89 7 0 0x88 7 0 is 0x002C To fix the RF_P2 RF_B1 and RF_B0 parameters use attribute code 0x002C and 0x006C in sequence 1 Use attribute code 0x002C and 0x85 7 0 0x84 7 0 set to 0x0109 The return value on registers 0x89 7 0 0x88 7 0 is the current fix status 2 Use attribute code 0x006C wit...

Page 185: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note Bit31 isalwayssetto 1to sendthemessage 0x201 0x200 0 PRBSPatternSelect 4 1 0x0 PRBS7 0x1 PRBS9 0x2 PRBS11 0x3 PRBS13 0x4 PRBS15 0x5 PRBS23 0x6 PRBS31 0xF DisablePRBS Loopback Option 0 External loopback 1 Internal loopback 0x203 0x202 SendMessage Reserved OPCODE SET_OPERATION_MODE 0x13 0 Figure 100 Loading PMA Configuration Register CHECK_CAL_STAT ...

Page 186: ...4 for PRBS15 0x200 4 1 4 h5 for PRBS23 0x200 4 1 4 h6 for PRBS31 0x200 4 1 4 hF to disable PRBS 0x201 7 0 8 h00 0x202 7 0 8 h00 0x203 7 0 8 h93 9 3 3 Start Adaptation and Put PMA in Mission Mode You can start initial and continuous adaptation and place the transceiver in mission mode 0x200 4 0 4 h6 0x201 0 0x200 7 5 4 h0 to set the PRBS generator and checker in PRBS7 mode after initial adaption is...

Page 187: ...3 0x203 7 0 0x96 9 3 4 Read the Physical Channel Number To read the physical channel number of the current channel on the E Tile 0x200 7 0 8 h00 0x201 7 0 8 h00 0x202 7 0 8 h00 0x203 7 0 8 h97 After writing to register 0x203 poll 0x207 7 until it becomes 1 The physical channel number is located on register 0x204 9 4 Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 Use the follo...

Page 188: ... 39 No No No No 52 Yes Yes Yes No 54 Yes Yes No No 55 Yes No No No 56 Yes Yes Yes No 58 Yes Yes No No 60 Yes Yes Yes No 62 Yes Yes No No 64 Yes Yes Yes Yes 65 Yes No No No 66 Yes Yes No No 68 Yes Yes Yes No 70 Yes Yes No No 72 Yes Yes Yes Yes 74 Yes Yes No No 75 Yes No No No 76 Yes Yes Yes No 78 Yes Yes No No 80 Yes Yes Yes Yes 82 Yes Yes No No 84 Yes Yes Yes No 85 Yes No No No continued 9 Registe...

Page 189: ... Yes No No 112 Yes Yes Yes Yes 114 Yes Yes No No 116 Yes Yes Yes No 118 Yes Yes No No 120 Yes Yes Yes Yes 122 Yes Yes No No 124 Yes Yes Yes No 125 Yes No No No 126 Yes Yes No No 128 Yes Yes Yes Yes 130 Yes Yes No No 132 Yes Yes Yes No 134 Yes Yes No No 135 Yes No No No 136 Yes Yes Yes Yes 138 Yes Yes No No 139 No No No No 140 Yes Yes Yes No 142 Yes Yes No No 144 Yes Yes Yes Yes 145 Yes No No No co...

Page 190: ...een RS FEC register reads should be at least 10 μs Table 63 RS FEC Registers Address Name Description Reset 0x04 rsfec_top_clk_cfg RS FEC Clock configuration register 0x0000 0F00 0x10 rsfec_top_tx_cfg RS FEC TX configuration register 0x0000 0000 0x14 rsfec_top_rx_cfg RS FEC RX configuration register 0x0000 0000 0x20 tx_aib_dsk_conf Defines the configuration fields for TX Deskew 0x0000 0000 0x30 rs...

Page 191: ...sfec_lane_rx_stat_3 0x160 rsfec_lane_rx_hold_0 RS FEC per lane RX status hold 0x0000 0000 0x164 rsfec_lane_rx_hold_1 0x168 rsfec_lane_rx_hold_2 0x16C rsfec_lane_rx_hold_3 0x170 rsfec_lane_rx_inten_0 RS FEC per lane RX status hold interrupt set to 1 to enable rsfec_lane_rx lane interrupt 0x0000 0000 0x174 rsfec_lane_rx_inten_1 0x178 rsfec_lane_rx_inten_2 0x17C rsfec_lane_rx_inten_3 0x180 rsfec_lane...

Page 192: ...corr_cw_cnt_0_hi RS FEC number of FEC codewords with errors that were corrected high word bits 63 to 32 0x0000 0000 0x20C rsfec_corr_cw_cnt_1_hi 0x214 rsfec_corr_cw_cnt_2_hi 0x21C rsfec_corr_cw_cnt_3_hi 0x220 rsfec_uncorr_cw_cnt_0_lo RS FEC number of FEC codewords that could not be corrected due to too many errors low word bits 31 to 0 0x0000 0000 0x228 rsfec_uncorr_cw_cnt_1_lo 0x230 rsfec_uncorr_...

Page 193: ..._cnt_1_lo 0x290 rsfec_corr_1s_cnt_2_lo 0x298 rsfec_corr_1s_cnt_3_lo 0x284 rsfec_corr_1s_cnt_0_hi RS FEC number of bits corrected 1 0 for the lane high word bits 63 to 32 0x0000 0000 0x28C rsfec_corr_1s_cnt_1_hi 0x294 rsfec_corr_1s_cnt_2_hi 0x29C rsfec_corr_1s_cnt_3_hi All statistic registers are 64 bits and you must do two 32 bit reads Intel recommends that you enable the shadow_req 3 0 in offset ...

Page 194: ...s HW Access Protection Reset 31 28 core_tx_pcs_bypass FEC TX Bypass Setting this bit enables elane tx bypass to XCVRIF This is one bit per lane bit0 lane0 RW RO 0x0 14 12 core_tx_in_sel3 RS FEC TX Select For Lane 3 Indicates which data to select for rsfec core TX input 3 b000 Select EHIP Core TX Data all lanes should have same selection 3 b001 Select EHIP Lane TX Data 3 b010 Select AIB Lane TX Dat...

Page 195: ...Access Protection Reset 31 28 loopback_tx2rx FEC RX Bypass Setting this bit enable loopback from TX RS FEC to RX RS FEC instead of getting from XcvrIf This is one bit per lane bit0 lane0 RW RO 0x0 13 12 core_rx_out_sel3 RS FEC RX Output Select For Lane 3 Indicates which data to select for rsfec core TX input All lanes should have same selection for EHIP and RS FEC_DIRECT_100G modes Does not work f...

Page 196: ... modes Does not work for TX Select of Elane and Loopback 2 b00 Bypass RS FEC RX paths data from XCVRIF fec pcs path normal bypass 2 b01 Select output of RS FEC RX 2 b10 Bypass RS FEC RX paths data from XCVRIF fec path for both ehip and elane 2 b11 Debug Mode Select Loopback from EHIP TX Data RW RO 0x0 9 5 4 tx_aib_dsk_conf Description Address Addressing Mode Defines the configuration fields for TX...

Page 197: ...otection Reset 3 rs544 Selects the RS encoder decoder mode 0 Use RS 528 514 1 Use RS 544 514 RW RO 0x0 2 indic_byp Bypass error indication to reduce latency 0 Sync headers in the 66b words extracted from uncorrectable FEC codewords are deliberately invalidated 1 66b words extracted from uncorrectable codewords are not explicitly marked bad When number of symbol errors in a block of 8192 consecutiv...

Page 198: ...al_done 1 Reports the total skew detected at the end of the deskew procedure 0 5 0 5 cycles of delay added to remove skew 6 7 error detected RO WO 0x0 0 tx_dsk_eval_done Deskew Complete Means Deskew procedure has completed RO WO 0x0 9 5 8 rsfec_debug_cfg Description Address Addressing Mode Extra config debug on fec_clock 0x108 32 bits The reset values in this table represents register values after...

Page 199: ...ssed RO WO 0x0 0 hdr_inv PCS TX 66b invalid sync header Not valid when transcoding is bypassed RO WO 0x0 9 5 10 rsfec_lane_tx_hold Register Name Description Address Addressing Mode rsfec_lane_tx_hold_0 RS FEC per lane TX status hold 0x130 32 bits rsfec_lane_tx_hold_1 0x134 rsfec_lane_tx_hold_2 0x138 rsfec_lane_tx_hold_3 0x13C The reset values in this table represents register values after a reset ...

Page 200: ...ction Reset 3 pace_inv PCS TX pacing violation When RSFEC_LANE_CFG rs544 0 pace_inv is never set When RSFEC_LANE_CFG rs544 1 pace_inv is set when there is more than 33 consecutive non idle cycles RW RO 0x0 2 resync PCS TX alignment codeword marker resync Not valid when RSFEC_LANE_CFG1 eng_cust_am_en 1 RW RO 0x0 1 blk_inv PCS TX 66b invalid block type Not valid when transcoding is bypassed RW RO 0x...

Page 201: ...not be corrected Restarts the synchronization RO WO 0x0 1 not_locked RX lane not locked Not locked to alignment codeword markers 100GE 128GFC 25GE or to FEC codewords 32GFC One entry per physical lane regardless of RSFEC_CORE_CFG frac RO WO 0x0 0 sf Incoming signal fail transceiver unable to lock to signal One entry per physical lane regardless of RSFEC_CORE_CFG frac RO WO 0x0 9 5 13 rsfec_lane_rx...

Page 202: ...1S 0x0 9 5 14 rsfec_lane_rx_inten Register Name Description Address Addressing Mode rsfec_lane_rx_inten_ 0 RS FEC per lane RX status hold interrupt set to 1 to enable rsfec_lane_rx lane interrupt 0x170 32 bits rsfec_lane_rx_inten_ 1 0x174 rsfec_lane_rx_inten_ 2 0x178 rsfec_lane_rx_inten_ 3 0x17C The reset values in this table represents register values after a reset has completed Bit Name Descript...

Page 203: ... but the alignment markers were not unique or the skew was too large This is an event signal so use not_align above instead to determine the alignment state Restarts the synchronization Only applicable when RSFEC_CORE_CFG frac none 100GE 128GFC RO WO 0x0 0 not_align RX lanes not aligned state Incoming signal fail RX lanes not all locked alignment markers not unique or skew too large Only applicabl...

Page 204: ... so use not_align above instead to determine the alignment state Restarts the synchronization Only applicable when RSFEC_CORE_CFG frac none 100GE 128GFC RW RO 0x0 0 not_align RX lanes not aligned state Incoming signal fail RX lanes not all locked alignment markers not unique or skew too large Only applicable when RSFEC_CORE_CFG frac none 100GE 128GFC RW RO 0x0 9 5 18 rsfec_ln_mapping_rx Register N...

Page 205: ...c_cw_pos_rx_1 0x1C4 rsfec_cw_pos_rx_2 0x1C8 rsfec_cw_pos_rx_3 0x1CC The reset values in this table represents register values after a reset has completed Bit Name Description SW Access HW Access Protection Reset 12 0 num Bit number of first bit in FEC codeword Only intended for debug of deterministic latency RO WO 0x0000 9 5 21 rsfec_core_ecc_hold Description Address Addressing Mode RS FEC SRAM EC...

Page 206: ...hit 8 consecutive bits out of these 66 are XOR ed with the pattern One entry per physical lane regardless of RSFEC_CORE_CFG frac RW RO 0x00 7 0 rate TX error injection rate for each physical lane Data is output towards the PMA 66 bits at a time not to be confused with 66b PCS symbols The value specifies the fraction of such 66b words to hit The unit is 1 256th so a value of say 7 causes 7 256th of...

Page 207: ...at were corrected low word bits 31 to 0 0x200 32 bits rsfec_corr_cw_cnt_1_lo 0x208 rsfec_corr_cw_cnt_2_lo 0x210 rsfec_corr_cw_cnt_3_lo 0x218 The reset values in this table represents register values after a reset has completed Bit Name Description SW Access HW Access Protection Reset 31 0 stat Statistics value RO WO 0x0000 0000 9 5 25 rsfec_corr_cw_cnt High Description Address Addressing Mode rsfe...

Page 208: ...high word bits 63 to 32 0x224 32 bits rsfec_uncorr_cw_cnt_1_hi 0x22C rsfec_uncorr_cw_cnt_2_hi 0x234 rsfec_uncorr_cw_cnt_3_hi 0x23C The reset values in this table represents register values after a reset has completed Bit Name Description SW Access HW Access Protection Reset 31 0 stat Statistics value RO WO 0x0000 0000 9 5 28 rsfec_corr_syms_cnt Low Register Name Description Address Addressing Mode...

Page 209: ...ption SW Access HW Access Protection Reset 31 0 stat Statistics value RO WO 0x0000 0000 9 5 30 rsfec_corr_0s_cnt Low Register Name Description Address Addressing Mode rsfec_corr_0s_cnt_0_lo RS FEC number of bits corrected 0 1 for the lane low word bits 31 to 0 0x260 32 bits rsfec_corr_0s_cnt_1_lo 0x268 rsfec_corr_0s_cnt_2_lo 0x270 rsfec_corr_0s_cnt_3_lo 0x278 The reset values in this table represe...

Page 210: ... bits rsfec_corr_1s_cnt_1_lo 0x288 rsfec_corr_1s_cnt_2_lo 0x290 rsfec_corr_1s_cnt_3_lo 0x298 The reset values in this table represents register values after a reset has completed Bit Name Description SW Access HW Access Protection Reset 31 0 stat Statistics value RO WO 0x0000 0000 9 5 33 rsfec_corr_1s_cnt High Register Name Description Address Addressing Mode rsfec_corr_1s_cnt_0_hi RS FEC number o...

Page 211: ...e description in the 0x000A Receiver Tuning Controls section Changed the description in the 0x0126 Read Receiver Tuning Parameters section 2018 07 18 Made the following changes Added the Name and Type columns and updated descriptions in the PMA Capability Register Map table Added new registers to the PMA AVMM Registers section Updated the description in the 0x0008 Internal or Serial Loopback and R...

Page 212: ...hanges Added information for clocking fractured FEC Added new protocol Channel PLL Updated PAM4 protocol formatting 2018 05 15 Made the following changes continued UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S a...

Page 213: ...nel Mode PMA Direct Dual Channel Mode and Precision Time Protocol PTP Placement Added a description screenshot and link to the E Tile Channel Placement Tool and Intel Stratix 10 PCG 2018 01 31 Initial release A E Tile Channel Placement Tool UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 213 ...

Page 214: ... channels of PMA direct PAM4 30 Gbps to 57 8 Gbps designs use 12 even PMA channels bonded out all 24 channels instantiated 24 core interfaces UG 20056 2019 02 04 Send Feedback Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries ...

Page 215: ... 12 even channels Two adjacent core interfaces for a single PAM4 channel PMA direct FEC mode is off B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 215 ...

Page 216: ...gate 100G Fractured 25G EHIP_TOP EHIP_TOP PMA Direct PMA Direct RS FEC Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect FPGA Core 11 10 9 8 7 6 5 4 3 2 1 0 RS FEC RS FEC PMA CH0 PMA CH1 PMA CH2 PMA CH3 PMA CH4 PMA CH5 PMA CH6 PMA CH7 PMA CH8 PMA CH9 PMA CH10 PMA CH11 10 10 8 10 8 6 1 0 3 2 6 8 8 10 6 0 2 4 0 2 4 4 0 2 B PMA Direct...

Page 217: ...ed 25G EHIP_TOP EHIP_TOP PMA Direct PMA Direct RS FEC Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect Interconnect FPGA Core 23 22 21 20 19 18 17 16 15 14 13 12 RS FEC RS FEC PMA CH12 PMA CH13 PMA CH14 PMA CH15 PMA CH16 PMA CH17 PMA CH18 PMA CH19 PMA CH20 PMA CH21 PMA CH22 PMA CH23 22 22 20 22 20 18 12 14 18 20 20 22 18 12 14 16 12 14 16 16 1...

Page 218: ... a New Intel Quartus Prime Pro Edition Design This design example uses Intel Quartus Prime Pro Edition software version 18 0 1 Click File New Project Wizard 2 Select a project folder then keep clicking Next until you see Family Device Board Settings 3 Select your device then keep clicking Next until you reach the end of the project settings then click Finish B PMA Direct PAM4 30 Gbps to 57 8 Gbps ...

Page 219: ... 3 Selecting the Configuration Clock Source Use this procedure to set the clock for the transceiver reset sequence TRS and local TRS LTRS blocks 1 Click Assignment Settings Device Board 2 Click the Device and Pin Options button B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 219 ...

Page 220: ... depending on your clock frequency s availability Figure 108 Configuration Clock Source Selection B 4 Instantiating the Transceiver Native PHY IP This procedure describes how to instantiate your Intel Stratix 10 E Tile Transceiver Native PHY IP core B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 220 ...

Page 221: ... configurations such as Transceiver configuration rules PMA direct or PMA direct high data rate PAM4 Number of data channels TX RX PMA modulation type NRZ or PAM4 TX RX PMA data rate TX RX PMA reference clock frequency B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide 221 ...

Page 222: ... greater than 30 Gbps two adjacent channels are combined to provide a single PAM4 channel So total 24 2 12 PAM4 channels Note You must set the TX PMA tab as well B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Intel Stratix 10 E Tile Transceiver PHY User Guide Send Feedback 222 ...

Page 223: ...n system Sources and Probes Intel FPGA IP This procedure describes how to instantiate the In System Sources and Probes Intel FPGA IP core This IP is used as a reset signal in Making the Top Level Connection 1 Type In system source in the IP Catalog search field B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Send Feedback Intel Stratix 10 E Tile Transceiver PHY User Guide...

Page 224: ...Top Level Connection on page 224 B 6 Making the Top Level Connection Follow this procedure to make your top level connection through RTL 1 Click File New then select Verilog HDL File 2 Write the RTL code to connect the blocks module pam4_12ch input wire pll_refclk0 pll_refclk0 clk input wire reset B PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation UG 20056 2019 02 04 Intel Stratix 10 E Tile Tra...

Page 225: ...rx_clkout rx_coreclkin clk rx_dl_async_pulse rx_dl_async_pulse rx_dl_async_pulse rx_dl_measure_sel rx_dl_measure_sel rx_dl_measure_sel rx_is_lockedtodata rx_is_lockedtodata rx_is_lockedtodata rx_parallel_data rx_parallel_data rx_parallel_data rx_pma_ready rx_pma_ready rx_pma_ready rx_ready rx_ready rx_ready rx_serial_data rx_serial_data rx_serial_data rx_serial_data rx_serial_data_n rx_serial_data...

Page 226: ... according to the guidelines provided in the Intel Stratix 10 GX MX TX SX Device Family Pin Connection Guidelines 2 Download the settings to the board by clicking the Programmer tool Figure 114 Programmer Tool 3 Click Auto Detect to detect devices then locate the Intel Stratix 10 device 4 Next to the Intel Stratix 10 device Click Change file to locate and add the sof file B PMA Direct PAM4 30 Gbps...

Page 227: ... use Transceiver Toolkit to perform transceiver debug operations Refer to the Intel Quartus Prime Pro Edition User Guide Debug Tools for more information about the Transceiver Toolkit Related Information Intel Quartus Prime Pro Edition User Guide Debug Tools B 9 1 Monitoring Transceiver Signals Signal Tap is a debug tool that allows you to monitor important transceiver related signals for example ...

Page 228: ...odes Figure 116 Signal Tap Setup Tab Setup Tab Added signals B 10 PMA Direct PAM4 30 Gbps to 57 8 Gbps Implementation Revision History Document Version Changes 2019 02 04 Made the following changes Updated GUI figures in Instantiating the Transceiver Native PHY IP 2018 07 18 Made the following changes Added further description and a link to the Transceiver Toolkit documentation in the Debug Tools ...

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