Intel SE7320SP2 - 800MHZ Ecc Ddr Xeon Technical Manual Download | Manualshive

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Functional Architecture

Intel® Server Boards SE7320SP2 and SE7525GP2

Revision

4.0

32

3.6.1.9 PCI

APIs

The system BIOS supports the INT 1Ah, AH = B1h functions as defined in the PCI BIOS
Specification. The system BIOS supports the real mode interfaces and does not support the
protected mode interfaces.

3.6.2

Split Option ROM

The BIOS supports the split option ROM algorithm per the PCI 3.0 specification.

3.6.3 Interrupt

Routing

The interrupt architecture accommodates both PC-compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the Intel 6300ESB I/O controller.

3.6.3.1

Legacy Interrupt Routing

For PC-compatible mode, the Intel 6300ESB I/O controller provides two 82C59-compatible
interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on
level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is
presented to the processors, to which only one processor will respond for servicing. The Intel
6300ESB I/O controller contains configuration registers that define which interrupt source
logically maps to I/O APIC INTx pins.

Interrupts, both PCI and IRQ types, are handled by the Intel 6300ESB I/O controller. The Intel
6300ESB I/O controller then translates these to the APIC bus. The numbers in the table below
indicate the Intel 6300ESB I/O controller PCI interrupt input pin to which the associated device
interrupt (INTA, INTB, INTC, INTD) is connected. The Intel 6300ESB I/O controller I/O APIC
exists on the I/O APIC bus with the processors.

Table 11. PCI Interrupt Routing/Sharing

Interrupt

INT A

INT B

INT C

INT D

Video PIRQB

Intel

®

82541 NIC

PIRQA

PCI Slot 3 (PCI 32b/33M)

PIRQF PIRQD PIRQB PIRQH

PCI Slot 5 (PCI 32b/33M)

PIRQE PIRQB PIRQH PIRQD

PCI Slot 2 (64b/66M)

PXIRQ1 PXIRQ2 PXIRQ3 PXIRQ0

PCI Slot 1 (64b/66M)

PXIRQ0 PXIRQ1

3.6.3.2

APIC Interrupt Routing

For APIC mode, interrupt architecture incorporates three Intel I/O APIC devices to manage and
broadcast interrupts to local APICs in each processor. The Intel I/O APICs monitor each
interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts
IRQ(0-15).

When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for

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Summary of Contents for SE7320SP2 - 800MHZ Ecc Ddr Xeon

Page 1: ...Intel Server Boards SE7320SP2 and SE7525GP2 Technical Product Specification Intel reference number D24635 004 Revision 4 0 December 2005 Enterprise Platforms and Services Division Marketing ...

Page 2: ...icular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserve...

Page 3: ... 3 1 5 Common Enabling Kit CEK Design Support 11 3 1 6 Processor Support 12 3 1 7 Multiple Processor Initialization 14 3 1 8 CPU Thermal Sensors 15 3 1 9 Processor Thermal Control Sensor 15 3 1 10 Processor Thermal Trip Shutdown 15 3 1 11 Processor IERR 15 3 2 Intel E7320 Chipset Intel Server Board SE7320SP2 15 3 2 1 Memory Controller Hub MCH 16 3 3 Intel E7525 Chipset Intel Server Board SE7525GP2...

Page 4: ...tem 30 3 6 2 Split Option ROM 32 3 6 3 Interrupt Routing 32 3 6 4 IDE Support 36 3 6 5 SATA Support 36 3 6 6 Video Controller 37 3 6 7 Network Interface Controller NIC 39 3 6 8 USB 2 0 Support 40 3 6 9 Super I O Chip 40 3 6 10 BIOS Flash 43 3 7 Configuration and Initialization 43 3 7 1 Memory Space 43 3 7 2 I O Map 50 3 7 3 Accessing Configuration Space 52 3 8 Clock Generation and Distribution 55 ...

Page 5: ... OEM Logo 86 4 8 OEM Binary 88 4 9 Operating System Boot Sleep and Wake 89 4 9 1 Microsoft Windows Compatibility 89 4 9 2 Advanced Configuration and Power Interface ACPI 89 4 9 3 Sleep and Wake Functionality 90 4 9 4 Power Switch Off to On 90 4 9 5 On to Off OS absent 91 4 9 6 On to Off OS present 91 4 9 7 System Sleep States 91 4 10 Security 92 4 10 1 Operating Model 93 4 10 2 Administrator User ...

Page 6: ...nt Message Reception 109 5 2 11 Event Filtering and Alerting 109 5 2 12 NMI Generation 112 5 2 13 SMI Generation 113 5 3 Platform Management Interconnects 113 5 3 1 Power Supply Interface Signals 113 5 3 2 System Reset Control 115 5 3 3 Temperature based Fan Speed Control 115 5 3 4 Front Panel Control 116 5 3 5 Secure Mode Operation 119 5 3 6 FRU Information 120 5 4 Sensors 121 5 4 1 Sensor Type C...

Page 7: ...Connector 141 7 2 Memory Module Connector 142 7 3 Processor Socket 143 7 4 I2 C Headers 146 7 5 PCI Slot Connector 147 7 6 Front Panel Connector 151 7 7 VGA Connector 152 7 8 NIC Connector 152 7 9 IDE Connector 153 7 10 SATA Connectors 153 7 11 USB Connector 154 7 12 Floppy Connector 155 7 13 Serial Port Connector 156 7 14 Keyboard and Mouse Connector 157 7 15 Miscellaneous Headers 157 7 15 1 Fan ...

Page 8: ...f Economic Development New Zealand Declaration of Conformity 169 9 2 4 BSMI Taiwan 169 9 3 Replacing the Back up Battery 169 Appendix A Integration and Usage Tips 171 Glossary 172 List of Figures Figure 1 Intel Server Board SE7320SP2 Layout 3 Figure 2 Intel Server Board SE7525GP2 Layout 6 Figure 3 Intel Server Board SE7320SP2 Block Diagram 8 Figure 4 Intel Server Board SE7525GP2 Block Diagram 9 Fi...

Page 9: ...12 Table 4 Supported DDR 266 DIMM Populations 24 Table 5 Supported DDR 333 DIMM Populations 25 Table 6 DIMM Module Capacities 25 Table 7 Possible Memory Capacities 25 Table 8 Suggested SEC Threashold Prescale Settings 27 Table 9 DIMM Threshold Values by DIMM Size 27 Table 10 PCI Bus Segment Characteristics 30 Table 11 PCI Interrupt Routing Sharing 32 Table 12 Interrupt Definitions 33 Table 13 Vide...

Page 10: ...b menu Selections 73 Table 36 BIOS Setup Boot Device Priority Sub menu Selections 74 Table 37 BIOS Setup Hard Disk Drive Sub Menu Selections 74 Table 38 BIOS Setup Removable Drives Sub menu Selections 74 Table 39 BIOS Setup CD DVD Drives Sub menu Selections 75 Table 40 BIOS Setup Security Menu Options 75 Table 41 BIOS Setup Server Menu Selections 76 Table 42 BIOS Setup System Management Sub menu S...

Page 11: ...nnectors J16 J18 J20 J21 142 Table 75 Socket 604 Processor Socket Pin out J36 J37 143 Table 76 HSBP Header Pin out J54 146 Table 77 HSBP Header Pin out J30 146 Table 78 Remote Management Card Header Pin out J33 147 Table 79 P32 A 5V 32 bit 33 MHz PCI Slot Pin out J10 J11 147 Table 80 P64 B 3 3V 64 bit 66 MHz PCI X Slot Pin out J8 J9 148 Table 81 PCI Express Slot Pin out J13 for x4 J14 for x16 149 ...

Page 12: ...J19 Pin out 158 Table 96 SCSI LED Header Pin out J26 158 Table 97 Configuration Jumper Options 159 Table 98 BIOS Bank Jumper Option 160 Table 99 Absolute Maximum Ratings 161 Table 100 MTBF Calculation 161 Table 101 Intel Xeon Processor DP TDP Guidelines 162 Table 102 Power Supply Voltage Specification 162 Table 103 Voltage Timing Parameters 163 Table 104 Turn On Off Timing 164 Table 105 Transient ...

Page 13: ... Chapter 5 Platform Management Chapter 6 Error Reporting and Handling Chapter 7 Connector Definitions and Pin outs Chapter 8 General Specifications Chapter 9 Product Regulatory Compliance 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high density VLSI and power delivery components which need adequate airflow to cool Intel ensures through its own chassis develo...

Page 14: ... 1 1 Intel Server Board SE7320SP2 Feature Set Dual processor slots supporting Intel Xeon processors operating at 800MT s system bus Intel E7320 chipset MCH 6300ESB Four DIMM slots supporting DDR 266 333 MHz memory Single Intel 82541 10 100 1000 Network Interface controller NIC Onboard ATI Rage XL video controller with 8 MB SDRAM Intel Server Management support External I O connectors Stacked PS2 p...

Page 15: ...ision 4 0 3 The following figure shows the board layout of the Intel Server Board SE7320SP2 Each connector and major component is identified by number and identified in Table 1 Figure 1 Intel Server Board SE7320SP2 Layout 1 1 2 3 4 5 6 7 8 8 9 10 11 12 13 14 15 1 17 1 19 ...

Page 16: ...able This section describes its feature set While similar to the Server Board SE7320SP2 there are specific features that make this server board suitable for an entry level workstation solution as well as an entry server environment 2 2 1 Intel Server Board SE7525GP2 Feature Set Dual processor slots supporting Intel Xeon processors operating on the 800MT s system bus Intel E7525 chipset MCH ICH5R F...

Page 17: ...ne x16 PCI Express graphics connector One x 8 PCI Express connector on x4 PCI Express bus Two 32 bit 33 MHz PCI connectors Two 64 bit 66 MHz PCI X connectors Intel Light Guided Diagnostics on most FRU devices processors memory Port 80 diagnostic LEDs displaying POST Codes The following figure shows the board layout of the Intel Server Board SE7525GP2 Each connector and major component is identifie...

Page 18: ...Server Board Overview Intel Server Boards SE7320SP2 and SE7525GP2 Revision 4 0 6 Figure 2 Intel Server Board SE7525GP2 Layout 1 1 2 3 4 5 6 7 8 8 9 10 11 12 13 14 15 1 17 1 19 20 ...

Page 19: ...1A 1B 12 PATA HDD connectors primary blue secondary white 3 Two external USB connectors 13 Floppy connector 4 Keyboard and mouse connector 14 Main jumper block 5 Stacked video and serial 15 Serial B header 6 Main power 16 12V CPU power 7 RJ 45 Gigabit NIC connector 17 Post Code LEDs 8 32 bit PCI slots 18 SATA connectors left to right A2 A1 9 PCI Express x8 connector x4 bus 19 Front panel USB heade...

Page 20: ...n of the functionality associated with the architectural blocks that make up the server boards Note Due to the similarities between these two products this chapter discusses all features that are present on both products Where appropriate features that are specific to one product or the other will noted Figure 3 Intel Server Board SE7320SP2 Block Diagram ...

Page 21: ... system The support circuitry for the processor sub system consists of the following Dual 604 pin zero insertion force ZIF processor sockets Processor host bus AGTL support circuitry Reset configuration logic Processor module presence detection logic BSEL detection capabilities CPU signal level translation Common enabling kit CEK CPU retention support ...

Page 22: ...nstruction All processors in the system must operate at the same frequency have the same cache sizes and same VID No mixing of product families is supported Processors run at a fixed speed and cannot be programmed to operate at a lower or higher speed 3 1 3 Processor Module Presence Detection The server boards provide logic to detect the presence and identity of installed processors In dual proces...

Page 23: ... kit CEK processor mounting and heatsink retention solution The server board will ship with a CEK spring snapped onto the underside of the board beneath each processor socket The CEK spring is removable allowing for the use of non Intel heatsink retention solutions Figure 5 CEK Processor Mounting Heatsink assembly with integrated hardware Thermal Interface Material TIM Server board CEK Spring Chas...

Page 24: ...Hz 3 4 GHz Yes Intel Xeon 800 MHz 3 6 GHz Yes Intel Xeon 800 MHz 3 8 GHz Yes Note The latest BIOS needs to be implemented before to have new Intel Xeon processors supported on these server boards See the Supported Processors List located on the support website for a complete list of supported processors http support intel com support motherboards server se7320sp2 http support intel com support mot...

Page 25: ... switches to set the processor frequency The BIOS reads the highest ratio register from all processors in the system If all processors are the same speed the Actual Ratio register is programmed with the value read from the High Ratio register If all processors do not match the highest common value between High and Low Ratio is determined and programmed to all processors If there is no value that w...

Page 26: ... enable this capability 3 1 6 12 Execute Disable Bit support The system BIOS supports the execute disable NX bit in the latest Intel Xeon processors This option can be enabled or disabled in the BIOS setup utility It is disabled by default to allow users to opt in to the protection this feature provides 3 1 7 Multiple Processor Initialization IA 32 processors have a microcode based boot strap proc...

Page 27: ...otect the processor the management controller automatically powers off the system In addition it will assert the System Status LED and generate an event in the system event log 3 1 11 Processor IERR The IERR signal is asserted by the Intel Xeon processor as a result of an internal error The mBMC configures the heceta7 device to monitor this signal When this signal is asserted the mBMC generates a ...

Page 28: ...memory stacked or unstacked Peak theoretical memory data bandwidth using DDR266 technology is 4 26 GB s and 5 33 GB s for DDR333 technology For DDR2 400 technology this increases to 6 4 GB s When both DDR channels are populated and operating they function in lock step mode For the Intel E7320 MCH the maximum supported memory size at DDR266 DDR333 or DDR2 400 memory configuration is 12 GB On the In...

Page 29: ...compliant with the same revision of the specification See the SE7320SP2 SE7525GP2 Tested Hardware and OS List for the adapters tested on those systems 3 2 1 4 Hub Interface The MCH interfaces with the Intel 6300ESB I O controller hub through a dedicated hub interface that supports a peak bandwidth of 266 MB s using a x4 base clock of 66 MHz The 6300ESB I O controller is discussed in further detail...

Page 30: ... or DDR2 400 memory stacked or unstacked Peak theoretical memory data bandwidth using DDR266 technology is 4 26 GB s and 5 33 GB s for DDR333 technology For DDR2 400 technology this increases to 6 4 GB s When both DDR channels are populated and operating they function in lock step mode For the Intel E7525 MCH the maximum supported memory size at DDR266 DDR333 or DDR2 400 is 12 GB On the Server Boa...

Page 31: ...320SP2 SE7525GP2 Tested Hardware and OS List for the add in cards tested on this platform 3 3 1 4 Hub Interface The MCH interfaces with the Intel 6300ESB I O controller hub via a dedicated hub Interface supporting a peak bandwidth of 266 MB s using a x4 base clock of 66 MHz 3 4 Intel 6300ESB ICH The Intel 6300ESB is a multi function device that provides an upstream hub interface for access to seve...

Page 32: ...d independently They can be configured to the standard primary and secondary channels four devices 3 4 3 SATA Controller The SATA controller supports two SATA devices providing an interface for SATA hard disks and ATAPI devices The SATA interface supports PIO IDE transfers up to 16 Mb s and Serial ATA transfers up to 1 5 Gb s 150 MB s The Intel 6300ESB I O controller SATA system contains two indep...

Page 33: ...6300ESB I O controller contains an Enhanced Host Controller Interface Specification for Universal Serial Bus Revision 1 0 compliant host controller that supports USB high speed signaling High speed USB 2 0 allows data transfers up to 480 Mb s which is 40 times faster than full speed USB The Intel 6300ESB I O controller also contains four universal host controller interface UHCI controllers that su...

Page 34: ...ite Byte Word Read Byte Word Process Call Block Read Write and Host Notify 3 5 Memory Sub System The MCH provides an integrated memory controller for direct connection to two channels of registered DDR266 or DDR333 memory stacked or unstacked Peak theoretical memory data bandwidth using DDR266 technology is 4 26 GB s and 5 33 GB s for DDR333 technology When both DDR channels are populated and oper...

Page 35: ... must be populated in pairs The server boards each have four DIMM slots or two DIMM banks Both DIMMs in a bank should be identical same manufacturer CAS latency number of rows columns and devices timing parameters etc Although DIMMs within a bank must be identical the BIOS supports various DIMM sizes and configurations allowing the banks of memory to be different Memory sizing and configuration is...

Page 36: ...ank locations on the server board Figure 6 DIMM Socket Configuration The following tables show supported memory populations Table identifiers S R single rank D R dual rank E Empty Table 4 Supported DDR 266 DIMM Populations DIMM Slot A2 DIMM Slot A1 DIMM Slot B2 DIMM Slot B1 E S R E E S R S R E E E D R E E D R D R E E D R S R E E ...

Page 37: ... MB 1 GB 2 GB 4 GB 2 1 GB 2 GB 4 GB 8 GB 4 X 1 GB 2 GB 4 GB 8 GB 4 X 2 GB 4 GB 8 GB Note Memory between 4 GB and 4 GB minus 512 MB is not be accessible for use by the operating system and may be lost to the user This area is reserved for BIOS APIC configuration space PCI adapter interface and virtual video memory space This means that if 4 GB of memory is installed 3 5 GB of this memory is usable ...

Page 38: ...4 1 Mechanism for CME SEC Counter The expected error rates for DIMMs are stated per gigabyte of memory This information comes from three sources Intel experimental measurements one and one half errors per year Data from a memory component vendor one error per month The results from a 10 year study by a major computer manufacturer four errors per month Since the lowest error rate was gathered over ...

Page 39: ...x 8 2 GB 4 x 16 4 GB 4 x 32 Example If the DIMM in socket 1A 256 MB its counter value is 08h If the CME count that occurs on this DIMM is over 08h then the DIMM 1A LED will be lit and the CME logging and detection will be disabled by BIOS If the DIMM in socket 2A is 512 MB its counter value is 10h If the CME count that occurs on this DIMM is over 10h then the DIMM 2A LED will be lit and the CME lo...

Page 40: ...rrors detected the scrub engine logs the failure Both types of errors may be reported via multiple alternate mechanisms under configuration control The scrub hardware will also execute demand scrub writes when correctable errors are encountered during normal operation on demand reads rather than scrub initiated reads This functionality provides incremental protection against time based deteriorati...

Page 41: ... E7320 MCH and Intel E7525 MCH include specialized hardware to support fail over to a spare DIMM device in the event that a primary DIMM in use exceeds a specified threshold of runtime errors One of the DIMMs installed per channel will not be used but kept in reserve In the event of significant failures in a particular DIMM it and its corresponding partner in the other channel if applicable will o...

Page 42: ... memory 3 6 I O Sub System The I O sub system is made up of several components the MCH providing the PCI Express interface and the Intel 6300ESB I O controller providing the interface for the onboard video controller Super I O chip and Management Sub system This section describes the function of each I O interface and how they operate on these server boards 3 6 1 PCI Subsystem The primary I O inte...

Page 43: ...of a bridge device in the chipsets Scanning continues on the secondary side of the bridge until all subordinate buses are defined PCI bus numbers may change when PCI PCI bridges are added or removed If a bridge is inserted in a PCI bus all subsequent PCI bus numbers below the current bus will be increased by one 3 6 1 6 Resource Assignment The resource manager assigns the PIC mode interrupt for th...

Page 44: ... define which interrupt source logically maps to I O APIC INTx pins Interrupts both PCI and IRQ types are handled by the Intel 6300ESB I O controller The Intel 6300ESB I O controller then translates these to the APIC bus The numbers in the table below indicate the Intel 6300ESB I O controller PCI interrupt input pin to which the associated device interrupt INTA INTB INTC INTD is connected The Inte...

Page 45: ...py disk IRQ7 Generic IRQ8_L Active low RTC interrupt IRQ9 SCI IRQ10 Generic IRQ11 Generic IRQ12 Mouse interrupt IRQ13 Floating point processor IRQ14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1 IRQ15 Secondary IDE cable SMI System management interrupt General purpose indicator sourced by the 6300ESB to the processors 3 6 3 4 Serialized IRQ Support The server boards support ...

Page 46: ...nternal IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 X16 PCI E interface Supported by SE7525GP2 only 6300ESB ICH I O APIC 6300ESB ICH MCH X4 PCI E interface 6300ESB ICH 8259PIC X8 connector X16 Connector CPU1 CPU2 INTR INTR HI1 5 INTERFACE ...

Page 47: ...SA Floppy ISA ISA RTC SCI ISA ISA ISA Mouse ISA Coprocessor Error P IDE ISA Not Used Cascade Serialized IRQ Interface SERIRQ SERIRQ Intel 6300ESB ICH Interrupt Routing PCI Interface Video INTA Slot 3 INTC Slot 5 INTB Intel 82541 INTA Slot 3 INTB Slot 5 INTD Slot 5 INTA Slot 3 INTA Slot 3 INTD Slot 5 INTC PCI X interface PXIRQ3 PXIRQ2 PXIRQ0 PXIRQ1 Slot 1 INTA Slot 2 INTD Slot 1 INTB Slot 2 INTA Sl...

Page 48: ...accessing the BIOS Setup Utility during POST The SATA function in the Intel 6300ESB I O controller has dual modes of operation to support different operating system conditions In the case of Native IDE enabled operating systems the Intel 6300ESB I O controller has separate PCI functions for serial and parallel ATA To support legacy operating systems there is only one PCI function for both the seri...

Page 49: ...nterface for the Intel RAID Technology implementation and provides the ability for an Intel RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume s attached to the Intel RAID controller 3 6 6 Video Controller Both server boards provide an ATI Rage XL PCI graphics accelerator along with 8 MB of video SDRAM and support circuitry for an e...

Page 50: ...Enabled 640x480 60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported Supported 1280x1024 43 60 70 72 Supported Supported 1600x1200 60 66 76 85 Supported 3D Mode Refresh Rate Hz 3D Video Mode Support with Z Buffer Disabled 640x480 60 72 75 90 100 Supported Supported Supported Su...

Page 51: ...single network interface The 82541 controller is capable of supporting 10 100 1000 operation and alert on LAN functionality The controller can be disabled by using the BIOS Setup Utility accessed during POST The 82541 supports the following features 32 bit PCI Rev 2 3 compliant master interface Integrated IEEE 802 3 10Base T 100Base TX and 1000Base TX compatible PHY IEEE 820 3ab auto negotiation s...

Page 52: ...ealth sensors fan monitoring and control and a chassis intrusion detector The PC87427 also incorporates a Floppy Disk controller FDC two serial ports UARTs a keyboard and mouse controller KBC General Purpose I O GPIO GPIO extension for additional off chip GPIO ports and an interrupt serializer for parallel IRQs PC87427 features 3 3V operation Standby powered Legacy modules FDC two Serial ports UAR...

Page 53: ...CI X Slot 1 GPIOE42 Standby Input Output PCIE_WAKE_N Input Wake up Event from PCI E Bus GPIOE43 Standby Input Output PME_N Intput PME from PCI Bus GPIOE44 SCI Standby Input Output SUPER IO_PME_N Output Active Low to generate a PME to the 6300ESB ICH GPIOE45 LED Standby Input Output PME_PCIX_N Input PME from PCI X Bus GPIO50 DCDM_N Standby Input Output NWY_DIS_N Output Active Low to disable Intel 8...

Page 54: ...ndard RS232 pin out as defined in the following table Table 16 Serial B Header Pin out Pin Signal Name Serial Port A Header Pin out 1 DCD 2 DSR 3 RX 4 RTS 5 TX 6 CTS 7 DTR 8 RI 9 GND 3 6 9 3 Floppy Disk Controller The 34 pin floppy disk controller FDC in the SIO is functionally compatible with floppy disk controllers in the DP8473 and N844077 All FDC functions are integrated into the SIO including...

Page 55: ...nvironment including address maps for memory and I O techniques and considerations for programming ASIC registers and hardware options configuration 3 7 1 Memory Space At the highest level the Intel Xeon processor address space is divided into four regions as shown in the following figure Each region contains sub regions as described in following sections Attributes can be independently assigned t...

Page 56: ...ntel Xeon Processor Memory address Space 4 GB Optional ISA Hole Top of Low Memory TOLM 16MB 15MB 1MB 640KB 512KB 0 Additional Main Memory Address Range Main Memory Address Range DOS Legacy Address Range Lo PCI Memory Space Range TSEG SMRAM S 64 GB Hi PCI Memory Address Range Upper Memory Ranges ...

Page 57: ...e region is divided into sub regions as shown in the following figure Figure 10 DOS Compatibility Region Mappable to PCI or ISA memory Main memory only PCI only Shadowed in main memory 000000h 07FFFFh 080000h 09FFFFh 0A0000h 0BFFFFh 0C0000h 0DFFFFh 0E0000h 0EFFFFh 0F0000h 0FFFFFh 1MB 960KB 896KB 768KB 640KB 512KB 0 System BIOS Extended System BIOS Add in Card BIOS and Buffer Area PCI ISA Video or ...

Page 58: ...0000h to 0DFFFFh is divided into eight segments of 16 KB segments mapped to ISA memory space each with programmable attributes for expansion cards buffers Historically the 32 KB region from 0C0000h to 0C7FFFh has contained the video BIOS location on the video card Extended System BIOS This 64 KB region from 0E0000h to 0EFFFFh is divided into four blocks of 16 KB each and may be mapped with program...

Page 59: ... addresses 0100000h to FFFFFFFh as shown in the following figure PCI memory space can be remapped to top of memory TOM Figure 11 Extended Memory Map Main Memory Address Region FFFFFFFFh FFE00000h FEC0FFFFh FEC00000h Top of Low Memory TOLM Depends on installed DIMMs 16 MB 15 MB 100000h High BIOS Area APIC Space Optional Fixed Memory Hole PCI Memory Space Extended chipset region 512KB Extended Syste...

Page 60: ...h BIOS The top 1 MB of Extended Memory under 4 GB is reserved for the system BIOS extended BIOS for PCI devices and A20 aliasing by the system BIOS The lntel Xeon processor begins executing from the high BIOS region after reset I O APIC Configuration Space A 64 KB block located 20 MB below 4 GB 0FEC00000 to 0FEC0FFFFh is reserved for the I O APIC configuration space The first I O APIC is located a...

Page 61: ...atible C A0000h to BFFFFh A0000h to BFFFFh High H 0FEDA0000h TO 0FEDBFFFFh A0000h to BFFFFh TSEG T TOLM TSEG_SZ to TOLM TOLM TSEG_SZ to TOLM Notes High SMM is different than in previous chipsets In previous chipsets the high segment was the 384 KB region from A_0000h to F_FFFFh However C_0000h to F_FFFFh was not useful so it is deleted in MCH TSEG SMM is different than in previous chipset In previ...

Page 62: ...DMA Controller 2 Aliased from 0000h 000Fh 0020h 0021h Interrupt Controller 1 0022h 0023h 0024h 0025h Interrupt Controller 1 Aliased from 0020 0021h 0026h 0027h 0028h 0029h Interrupt Controller 1 Aliased from 0020h 0021h 002Ah 002Bh 002Ch 002Dh Interrupt Controller 1 Aliased from 0020h 0021h 002Eh 002Fh Super I O SIO index and Data ports 0030h 0031h Interrupt Controller 1 Aliased from 0020h 0021h 0...

Page 63: ...r 2 aliased 00ACh 00ADh Interrupt Controller 2 aliased 00B0h 00B1h Interrupt Controller 2 aliased 00B4h 00B5h Interrupt Controller 2 aliased 00B8h 00B9h Interrupt Controller 2 aliased 00BCh 00BDh Interrupt Controller 2 aliased 00C0h 00DFh DMA Controller 2 00F0h Clear NPX error Resets IRQ13 00F8h 00FFh X87 Numeric Coprocessor 0102h Video Display Controller 0170h 0177h Secondary Fixed Disk Controlle...

Page 64: ...es contain PCI configuration space accessed using mechanism 1 defined in the PCI Local Bus Specification If dual processors are used only the processor designated as the boot strap processor BSP should perform PCI configuration space accesses Precautions should be taken to guarantee that only one processor performs system configuration Two Dword I O registers in the chipset are used for the config...

Page 65: ...f the last hierarchical PCI bus under the current bridge The PCI Bus Number and the Subordinate PCI Bus Number are the same in the last hierarchical bridge 3 7 3 1 2 Device Number and IDSEL Mapping Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus address data signals AD 31 11 for the PCI bus Each IDSEL mapped AD bit acts as a chip select for each device on...

Page 66: ...1 03 ICH5R USB UHCI controller 1 00 29 00 ICH5R USB UHCI controller 2 00 29 01 ICH5R USB UHCI controller 3 00 29 02 ICH5R USB 2 0 EHCI controller 00 29 07 FL Slot1 64 bit PCIX 100 P1A_AD17 01 FL Slot2 64 bit PCI X 100 P1A_AD18 02 FL Slot3 64 bit PCI X 100 P1A_AD19 03 FL PXH D Slot1 P2A_AD17 01 FL PXH D Slot 2 P2B_AD17 01 FL PCI E x4 Slot1 FL PCI E x4 Slot2 LP Slot1 64 bit PCI X 100 P1B_AD17 01 LP ...

Page 67: ... CK409B For DB800 clock buffer 100 MHz differential Clock at 0 7 V logic levels on DB800 For PCI Express Device is MCH And for SATA is Intel 6300ESB 66 MHz at 3 3 V logic levels For MCH and Intel 6300ESB 48 MHz at 3 3V logic levels For Intel 6300ESB and SIO 33 MHz at 3 3V logic levels For Intel 6300ESB Video BMC and SIO 14 318 MHz at 2 5 V logic levels For Intel 6300ESB and video 10 MHz at 5V logi...

Page 68: ...The EFI is the extensible firmware interface This is an abstraction layer between the operating system and system hardware Server BIOS extensions Support for Baseboard Management controller BMC and Intelligent Platform Management Interface IPMI Processor Microcode Updates The BIOS also includes latest processor microcode updates 4 1 BIOS Identification String The BIOS Identification string is used...

Page 69: ...ash screen can be customized by with the Change Logo utility Refer to the Change Logo for AMIBIOS User s Guide Version 2 22 for details 4 2 1 User Interface During the system boot up POST process there are two types of consoles used for displaying the user interface graphical or text based Graphics consoles are in 640x480 mode text consoles use 80x25 mode The console output is partitioned into thr...

Page 70: ...the BIOS displays a logo splash screen If not the BIOS displays a system summary and diagnostic screen in verbose mode The default is to display the logo in Quiet Boot mode If no logo is present in the flash ROM or Quiet Boot mode is disabled in the system configuration the summary and diagnostic screen is displayed If the user presses Esc the system transfers from the logo screen to the diagnosti...

Page 71: ...overs up any diagnostic messages in the middle section of the screen While the logo is being displayed on the local console diagnostic messages are being displayed on the remote text consoles Quiet Boot may be disabled by clearing the Setup Quiet Boot option or by the user pressing the Esc key while in Quiet Boot mode If Quiet Boot is disabled the BIOS displays diagnostic messages in place of the ...

Page 72: ...French German and Italian Intel provides translations for console strings in the supported languages The language can be selected using BIOS user interface 4 3 2 Console Redirection The BIOS Setup utility is functional via console redirection over various terminal standards emulation This may limit some functionality for compatibility e g usage of colors or some keys or key sequences or support of...

Page 73: ...is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a sub menu or pick list is displayed Tab Select Field The Tab key is used to move between fields For example Tab can be used to...

Page 74: ... Options Feature Options Help Text Description System Overview AMI BIOS Version N A N A BIOS ID string excluding the build time and date Build Date N A N A BIOS build date Processor Type N A N A Processor brand ID string Speed N A N A Calculated processor speed Count N A N A Detected number of physical processors System Memory Size N A N A Amount of physical memory detected Server Board MCH Steppi...

Page 75: ...ects submenu Memory Configuration N A Configure memory devices Selects submenu 4 4 2 1 Processor Configuration Sub menu Table 24 BIOS Setup Processor Configuration Sub menu Options Feature Options Help Text Description Configure Advanced Processor Settings Manufacturer Intel N A Displays processor manufacturer string Brand String N A N A Displays processor brand ID string Frequency N A N A Display...

Page 76: ...S Disabled Enabled Enabling adds secondary processor threads to the MPS Table for pre ACPI OSes Only enable this feature if the pre ACPI OS supports Hyper Threading Technology Intel SpeedStep Tech Disabled Auto Select disabled for maximum CPU speed Select enabled to allow the OS to reduce power consumption Visible only if the processor has this feature Execute Disable Bit Disabled Enabled Intel s ...

Page 77: ...ort0 to third IDE Master channel Port1 to fourth IDE Master channel Otherwise set SATA Port0 to fourth IDE Master channel and Port1 to third IDE Master channel Mixed PATA SATA N A Lets you remove a PATA and replace it by SATA in a given channel Only 1 channel can be SATA Selects submenu for configuring mixed PATA and SATA Primary IDE Master N A While entering setup BIOS auto detects the presence o...

Page 78: ...er spin up times ATA PI 80Pin Cable Detection Host Device Host Device Select the mechanism for detecting 80 pin ATA PI cable The 80 pin cable is required for UDMA 66 and above The BIOS detects the cable by querying the host and or device Table 26 Mixed PATA SATA Configuration with only Primary PATA Feature Options Help Text Description Mixed PATA SATA First ATA Channel PATA M S SATA M S Configure ...

Page 79: ...de S M A R T N A N A Display S M A R T support Type Not Installed Auto CDROM ARMD Select the type of device connected to the system The auto setting is correct in most cases LBA Large Mode Disabled Auto Disabled Disables LBA Mode Auto Enabled LBA Mode if the device supports it and the device is not already formatted with LBA Mode disabled The auto setting is correct in most cases Block Multi Secto...

Page 80: ...ng analysis and reporting technology The auto setting is correct in most cases 32Bit Data Transfer Disabled Enabled Enable disable 32 bit data transfer 4 4 2 3 Floppy Configuration Sub menu Table 28 BIOS Setup Floppy Configuration Sub menu Selections Feature Options Help Text Description Floppy Configuration Floppy A Disabled 720 KB 3 1 2 1 44 MB 3 1 2 2 88 MB 3 1 2 Select the type of floppy drive...

Page 81: ...tions Feature Options Help Text Description USB Configuration USB Devices Enabled N A N A List of USB devices detected by BIOS USB Function Disabled Enabled Enables USB HOST controllers When set to disabled other USB options are unavailable Legacy USB Support Disabled Keyboard only Auto Keyboard and Mouse Enables support for legacy USB Auto disables legacy support if no USB devices are connected I...

Page 82: ...if a device is detected includes a DeviceID string returned by the USB device Emulation Type Auto Floppy Forced FDD Hard Disk CDROM If Auto USB devices less than 530 MB will be emulated as floppy and remaining as hard drive Forced FDD option can be used to force a HDD formatted drive to boot as FDD Ex ZIP drive Device n N A N A Only displayed if a device is detected includes a DeviceID string retu...

Page 83: ...disable memory mapped I O of 64 bit PCI devices to 4 GB or greater address space MMIO below PCI Express MMCFG Enabled Disabled Disabled Highest PCI address set just below 4 GB for memory allocation but not compatible for all configurations with a PCI bridge aperture that spans PCI Express MMCFG space 3 5 3 75 GB Enabled Highest PCI address set to 3 5 GB just below PCI Express MMCFG Slot 1 Option R...

Page 84: ... Not Installed Disabled Spare Informational display DIMM 2B Installed Not Installed Disabled Spare Informational display Extended Memory Test 1 MB 1 KB Every Location Disabled Settings for extended memory test Memory Retest Disabled Enabled If Enabled BIOS will activate and retest all DIMMs on the next system boot This option will automatically reset to Disabled on the next system boot Memory Rema...

Page 85: ...ttings Configuration Sub menu Selections Table 35 BIOS Setup Boot Settings Configuration Sub menu Selections Feature Options Help Text Description Boot Settings Configuration Quick Boot Disabled Enabled Allows BIOS to skip certain tests while booting This will decrease the time needed to boot the system Quiet Boot Disabled Enabled Disabled Displays normal POST messages Enabled Displays OEM Logo in...

Page 86: ... that is listed in the boot menu is changed or removed Return to this menu any time a configuration change is made to a bootable controller card 4 4 3 2 1 Hard Disk Drive Sub menu Selections Table 37 BIOS Setup Hard Disk Drive Sub Menu Selections Feature Options Help Text Description Hard Disk Drives 1 st Drive Varies Specifies the boot sequence from the available devices Varies based on system co...

Page 87: ...word This option is grayed our when entering setup with a user password Set User Password N A Set or clear User password Pressing enter twice will clear the password User Access Level No Access View Only Limited Full Access No access prevents User access to the Setup Utility View Only allows access to the Setup Utility but the fields can not be changed Limited allows only limited fields to be chan...

Page 88: ... password is required to boot from diskette This node is grayed out if a user password is not installed Front Panel Switch Inhibit Disabled Enabled When disabled allows the use of Front Panel Switch When enabled inhibits Power Switch and Reset Switch button Disables the Power Switch and the Reset Switch when Secure mode is activated This node is grayed out if a password is not installed or if the ...

Page 89: ...detection The system is reset on timeout Hard Disk OS Boot Timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes This controls the time limit allowed for booting an operating system from a Hard disk drive The action taken on timeout is determined by the OS Watchdog Timer policy setting PXE OS Boot Timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes This controls the time limit allowe...

Page 90: ...Serial Number N A N A Field contents varies Chassis Part Number N A N A Field contents varies Chassis Serial Number N A N A Field contents varies BIOS Version N A N A BIOS ID string excluding the build time and date BMC Device ID N A N A Field contents varies BMC Firmware Revision N A N A Field contents varies BMC Device Revision N A N A Field contents varies PIA Revision N A N A Field contents va...

Page 91: ...e to a remote ANSI terminal Enabling this option disables Quiet Boot Baud Rate 9600 19 2K 38 4K 57 6K 115 2K N A Flow Control No Flow Control CTS RTS XON XOFF CTS RTS CD If enabled it will use the Flow control selected CTS RTS Hardware XON XOFF Software CTS RTS CD Hardware Carrier Detect for modem use Terminal Type PC ANSI VT100 VT UTF8 VT100 selection only works for English as the selected langua...

Page 92: ...vent Logging Disabled Enabled If enabled BIOS will detect and log events for system critical errors Critical errors are fatal to system operation These errors include PERR SERR ECC Enable SMM handlers to detect and log events to SEL ECC Event Logging Disabled Enabled Enables or disables ECC event logging Grayed out if Critical Event Logging option is disabled PCI Error Logging Disabled Enabled Ena...

Page 93: ...and video controllers It also contains support for the rolling single boot BIOS update feature The complete ROM is visible starting at physical address 4 GB minus the size of the flash ROM device The Flash Memory Update utility loads the BIOS image minus the recovery block to the secondary flash partition and notifies the BIOS that this image should be used on the next system re boot Because of sh...

Page 94: ...ting a rollback If a user wishes to force the system to boot to the primary bank the jumper at J29 can be used In the default jumper position with pins 1 2 covered the rolling BIOS configuration is automatic If the jumper is moved to cover pins 2 3 then the system will boot to the primary bank every time The rolling one boot update feature applies to all the update mechanisms discussed in the foll...

Page 95: ...sk contains both the ROM image and the afudos update utility Boot to DOS Run the afudos utility as follows AFUDOS i ROM filename n p b n c 4 7 1 2 Updating the BIOS from Microsoft Windows 2000 2003 XP Make sure that the flash disk contains the ROM image AMIFLDRV SYS and AFUWIN EXE Boot to Microsoft Windows 2000 2003 XP Run the AFUWIN utility as follows AFUWIN i ROM filename n p b n c 4 7 1 3 Updat...

Page 96: ...e for the UbinD utility is as follows UBinD R or I or D M ModID F RomFileName B NewUserBinaryFileName N NewRomFileName O NCB Where R replaces the user binary module I inserts the user binary module D deletes the user binary module from the ROM file displays help information M ModID is hexadecimal user binary module ID Default ModID 0xF0 O NCB is the 0 based index of the non critical block number c...

Page 97: ...ions of the secondary BIOS will be updated during the recovery process If an OEM wishes to preserve the OEM section across an update it is recommended that the OEM modify the provided AMIBOOT ROM file with the user binary or OEM logo tools before performing the recovery A BIOS recovery can be accomplished from one of the following devices a standard 1 44 or 2 88 MB floppy drive an USB Disk On Key ...

Page 98: ...on the floppy disk it beeps once for one second and then searches again After the beep load the second floppy disk The system will continue reading and searching for files Once a file has been read the system will increment the file extension and then begin searching for the next file If searching for the AMIBOOT 002 file the system will beep twice each beep for one second with a 0 5 second gap be...

Page 99: ...size up to 640x480 even width 256 color BMP 640x480 JPEG 640x480 800x600 or 1024x768 256 color PCX 640x480 Note The Rombuild exe file is NOT the same for DOS and Microsoft Windows 2000 2003 XP The user must use the correct Rombuild exe file for the operating system 4 7 4 1 Changing the OEM Logo for DOS 1 Boot to DOS 2 Download OEMLOGOD exe Rombuild exe RomFile and NewOEMlogoImage to the hard drive...

Page 100: ...n the first Megabyte The user binary code should not make any assumptions about the value of the code segment User binary code will always be executed from RAM and never from flash The code in user binary should not hook critical interrupts should not re program the chipset and should not take any action that affects the correct functioning of the system BIOS The BIOS copies the user binary into s...

Page 101: ...ystem through a series of tables located throughout memory The format and location of these tables is documented in the publicly available ACPI specification To prevent conflicts with a non ACPI aware operating system the memory used for the ACPI tables is marked as reserved in the INT 15h function E820h As described in the ACPI specification an ACPI aware operating system generates an SMI to requ...

Page 102: ...bits via the DSDT table The S5 state is equivalent to operating system shutdown No system context is saved 4 9 3 Sleep and Wake Functionality The BIOS supports a front panel power button The power button is a request that is forwarded by the mBMC to the ACPI power state machines in the chipset It is monitored by the mBMC and does not directly control power on the power supply The platform supports...

Page 103: ...tate if any the system transitions into 4 9 7 System Sleep States The platform supports the following ACPI system sleep states ACPI S0 working state ACPI S1 sleep state ACPI S4 suspend to disk state ACPI S5 soft off state The platform supports the following wake up sources in an ACPI environment As noted above the OS controls the enabling and disabling of these wake sources Devices that are connec...

Page 104: ...ing system configuration using the BIOS setup menu The maximum length of the password is seven characters The password cannot have characters other than alphanumeric a z A Z 0 9 Once set a password can be cleared by entering the password change mode and pressing enter twice without inputting a string All setup fields can be modified when entering the administrator password The user access level se...

Page 105: ...s to boot from drive A If the user enters correct password and drive A is bootable the system boots normally Password on boot Power On Reset User Password set and password on boot enabled and Secure Boot Disabled in setup System halts for user Password before scanning option ROMs The system is not in secure mode No mouse or keyboard input is accepted except the password User Password Admin Passwor...

Page 106: ...talled User Password Is Installed Login Type Admin Supervisor Set Admin Password visible Set User Password visible User Access Level Full visible Clear User Password visible Login Type User Set Admin Password hidden Set User Password visible User Access Level Full Shaded Clear User Password hidden Scenario 3 Administrator Password Is Installed User Password Is Not Installed Login Type Supervisor S...

Page 107: ...index htm 4 11 1 EFI Shell The EFI Shell is a special type of EFI application that allows EFI commands and other EFI applications to be launched The BIOS implements an EFI shell in flash and the shell can be invoked from the BIOS provided EFI environment The EFI shell provided in flash implements all the commands specified in the EFI1 1ShellCommands pdf document that comes with the EFI sample impl...

Page 108: ..._Core 12V 3 3 S B Vcc SCSI_term1 SCSI_term2 RTD RTD P12V_SCALED P_VT P5V P12V_CPU_SCALED DDR Core DDR Gb LAN Core VID_CPU0 5 0 VID_CPU1 5 0 P3V3_STBY P1V P3V P_VCCP0 P_VCCP1 P1V8_SCSI N12V_SCALED FET AM FA Zone Zone GTL to translation Logic GTL to translation Logic GTL to translation Logic Not Used Not Used SCSIB_TERMPWR SCSIA_TERMPWR GTL to translation Logic Tach Tach FA SECURE_MODE_KB CHASSIS IN...

Page 109: ...oftware and the platform management subsystem and a common set of messages commands for performing operations such as accessing temperature voltage and fan sensors setting thresholds logging events controlling a watchdog timer etc IPMI also includes a set of records called sensor data records SDRs that make the platform management subsystem self descriptive to system management software The SDRs i...

Page 110: ...ation to link sensors with the entity and or FRU they are associated with Information in the SDRs is also used for configuring and restoring sensor thresholds and event generation whenever the system powers up or is reset This is accomplished via a process called the initialization agent The mBMC reads the SDRs and based on bit settings writes the threshold data Then it enables event generation fo...

Page 111: ...ed platform event filtering or PEF The management controller includes recovery control functions that allow local or remote software to request actions such as power on off power cycle and system hard resets plus an IPMI watchdog timer that can be used by BIOS and run time management software as a way to detect software hangs The management controller provides out of band remote management interfa...

Page 112: ...following are the common features supported by the mBMC Power system System reset control System initialization Watchdog timer System event log Sensor data record SDR repository Field replaceable unit FRU inventory device NMI generation SMI generation Self test Secure mode Boot options ...

Page 113: ...and communicating with other systems and devices via various external interfaces The following figure is a block diagram of the mBMC as it is used in a server management system The external interface blocks to the mBMC are the discrete hardware peripheral device interface modules Figure 14 mBMC in a Server Management System SMBus mBMC ASIC Bus Interface Unit SMBus GPIO Pins one SMBus Interfaces Fl...

Page 114: ...lave SMBus interface It interfaces with the LAN On Motherboard LOM and peripherals through the two independent master bus interfaces 5 2 3 External Interface to mBMC Figure 15 shows the data control flow to and within the functional modules of the mBMC External interfaces from the host system LOM and peripherals interact with the mBMC through the corresponding interface modules as shown The mBMC c...

Page 115: ...munication interfaces Host SMS interface via SMBus interface LAN interface using the LAN On Motherboard SMBus 5 2 4 1 Channel Management The mBMC supports two channels System interface 802 3 LAN Table 48 Supported Channel Assigments Channel Id Media type Interface Supports Sessions 1 802 3 LAN IPMB 1 0 Multi sessions 2 System Interface IPMI SMBus Session less 5 2 4 2 User Model The mBMC supports o...

Page 116: ...ral device communication or if a response to the host request is not yet ready the mBMC does not acknowledge the device address NAK This forces the host software to stop and restart the session For more information on read write through SMBus see the System Management Bus SMBus Specification 2 0 5 2 4 5 LAN Interface The server board supports one DPC LAN interface via a UDP port 26Fh The mBMC supp...

Page 117: ...access BMC configuration access Remote NMI generation Ability to transfer IPMI messages between the LAN interface and other interfaces such as the System Interface IPMB and PCI SMBus This capability enables messages to be delivered to system management software and provides the ability to access sensors and FRU information on other management controllers IPMI Messages are encapsulated in a packet ...

Page 118: ...ications The following table presents the minimum support that will be provided Note that system management software and utilities may not use all the available management controller options and capabilities For detailed technical information on the operation of the LAN channel operation and LAN Alerting refer to Intelligent Platform Management Interface v1 5 specification Table 50 LAN Channel Spe...

Page 119: ...pability This capability can only be directed to one IP Address at a time Thus the boot flags and boot initiator information are also used to tell the BIOS where to send LAN Console Redirection 5 2 6 Wake On LAN Power On LAN and Magic Packet Support The server board supports Wake On LAN Power On LAN capability using the onboard network interface chips or an add in network interface card An add in ...

Page 120: ...internal timestamp clock used by the SEL and SDR subsystems This clock is incremented once per second It is read using the Get SEL Time command and set using the Set SEL Time command The Get SDR Time command can also be used to read the timestamp clock These commands are specified in the Intelligent Platform Management Interface Specification Version 1 5 After a mBMC reset or power up the mBMC set...

Page 121: ... Management Interface Specification Version 1 5 When the mBMC initializes or when the system boots the initialization agent scans the SDR repository and configures the sensors referenced by the SDRs This includes setting sensor thresholds enabling disabling sensor event message scanning and enabling disabling sensor event messages 5 2 10 Event Message Reception The mBMC supports externally e g BIO...

Page 122: ...ed from delayed to non delayed or an action whose delay time has been reduced has a higher priority Each generated event is logged by SEL Table 51 PEF Action Priorities Action Priority Delayed Type Note Power down 1 Yes PEF Action Soft shut down 2 Yes OEM PEF Action Not executed if a power down action was also selected Power cycle 3 Yes PEF Action Not executed if a power down action was also selec...

Page 123: ...nt as SNMP traps in ASF formatted Platform Event Traps to a specified alert destination The Alert over LAN feature is used to send either Platform Event Trap alerts or directed events to a remote system management application regardless of the state of the host s operating system LAN alerts may be sent over the LAN channel specified for the platform LAN alerts can be used by PEF to send out alerts...

Page 124: ...ement controller 5 2 12 NMI Generation The following may cause the mBMC to generate an NMI pulse Receiving a Chassis Control command issued from one of the command interfaces Use of this command will not cause an event to be logged in the SEL Detecting that the front panel Diagnostic Interrupt NMI button has been pressed A PEF table entry matching an event where the filter entry has the NMI action...

Page 125: ...bsystem indicates current the power state asserted power is on Figure 17 shows the power supply control signals and their sources To turn the system on the mBMC asserts the Power On signal and waits for the Power Good signal to assert in response indicating that DC power is on mBMC Power Sub System Power Good Power ON Figure 17 Power Supply Control Signals The mBMC uses the Power Good signal to mo...

Page 126: ...by one of the event occurrences listed in Table 53 and proceeds as follows The mBMC asserts system reset de asserts Power Good If enabled the mBMC sends a Set ACPI Power State command indicating an S0 state to all management controllers whose SDR management device records indicate that they should receive the notification The mBMC de asserts the Power On signal The power subsystem turns off system...

Page 127: ...ctions taken by the system Table 54 System Reset Sources and Actions Reset Source System Reset mBMC Reset 1 Standby power comes up No no DC power Yes 2 Main system power comes up Yes No 3 Reset button or in target probe ITP reset Yes No 4 Warm boot example DOS Ctrl Alt Del Yes No 5 Command to reset the system Yes No 6 Set Processor State command Yes No 7 Watchdog timer configured for reset Yes No ...

Page 128: ...n System ID LED Status Fault LED and Chassis Intrusion Switch Front panel control also includes the front panel lockout features 5 3 4 1 Power Button After de bouncing the front panel Power Button signal the mBMC routes the signal state directly to the chipset Power Button signal input If the chipset has been initialized by the BIOS the chipset responds to the assertion of the signal by requesting...

Page 129: ...ted to the button press duration This generates an event NMI button sensor and PEF OEM action causes NMI generation 5 3 4 4 Chassis ID Button and LED The front panel interface supports a Chassis Identify Button and a corresponding Blue Chassis Identify LED A second Blue Chassis Identify LED is mounted on the back edge of the server board where it may be visible when viewed from the back of an inte...

Page 130: ...link Non Critical Failure non critical fan voltage temperature state Off Solid Not Ready POST error NMI event CPU or terminator missing Critical Condition Any critical or non recoverable threshold crossing associated with the following events Temperature voltage or fan critical threshold crossing Power subsystem failure The BMC asserts this failure whenever it detects a power control fault e g the...

Page 131: ...ssis Intrusion offset 5 3 4 7 Front Panel Lockout The management controller monitors a Secure Mode signal from the keyboard controller on the server board When the Secure Mode signal is asserted the management controller may lock out the ability to power down or reset the system using the power or reset push buttons respectively Secure Mode may also block the ability to initiate a sleep request us...

Page 132: ...ined as any circuit board in the system containing active electronic circuitry FRU information includes board serial number part number name asset tag and other information FRUs that contain a management controller use the controller to provide access to the FRU information FRUs that lack a management controller can make their FRU information available via a SEEPROM directly connected to the IPMB ...

Page 133: ...pper nonrecoverable upper critical upper noncritical lower nonrecoverable lower critical lower noncritical uc lc upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors The offsets can be found in the Generic Event Reading Type Codes or Sensor Type Codes tables in the IPMI specification depending on whether the sensor event reading type is gene...

Page 134: ...on Reset Button As Trig Offset Watchdog 05h Watchdog2 23h Sensor Specific 6Fh Timer Expired Hard Reset Power Down Power cycle Timer Interrupt As Trig Offset The following table shows the server board platform sensors that are supported by the mBMC Table 58 Built in Platform Sensors Sensor Name Sensor Sensor Type Event Reading Type Event Offset Triggers Assert Deassert Readable Value Offsets Event ...

Page 135: ...nsor Sensor Type Event Reading Type Event Offset Triggers Assert Deassert Readable Value Offsets Event Data PEF Action SDR Record Type Physical Security Violation 09h Physical Security 05h Sensor Specific 6Fh General Chassis Intrusion As General Chassis Intrusion Trig Offset X 02 CPU1 12v 0Ah Voltage 02h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 CPU2 12v 0Bh Voltage 02h Thresh...

Page 136: ...h Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Tach Fan 2 Front 2 18h Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Tach Fan 3 Front 3 19h Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Tach Fan 4 Front 4 1Ah Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Tach Fan 5 Rear 1 1Bh Fan 04h Threshold 01h u...

Page 137: ...dentify Button 24h Button 14h Generic 03h Sate Deasserted State Assert As Trig Offset ID LED Action 02 Proc1 Fan 25h Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Proc2 Fan 26h Fan 04h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Proc1 Core temp 27h Temp 01h Threshold 01h u l nr c nc As De Analog R T Fault LED Action 01 Proc2 Core temp 28h Temp 01h Thresh...

Page 138: ...rors System errors can be categorized as follows PCI bus Memory multi bit errors single bit errors are not logged Sensors Processor internal errors bus address errors thermal trip errors temperatures and voltages and GTL voltage levels Errors detected during POST logged as POST errors Sensors are managed by the mBMC The mBMC is capable of receiving event messages from individual sensors and loggin...

Page 139: ...mory array if ECC memory is installed The SMI handler records the error and the DIMM location to the system event log Double bit errors in the memory array are mapped to the SMI because the mBMC cannot determine the location of the bad DIMM The double bit errors may have corrupted the contents of SMRAM The SMI handler will log the failing DIMM number to the mBMC if the SMRAM contents are still val...

Page 140: ...tem software IDs in the range 0x10 0x1f are reserved for the SMI handler The IPMI specification reserves two distinct ranges for the BIOS and the SMI handler Since the distinction between the two is not very important we use the same values of generator ID s for the BIOS as well as the SMI handler Technically the FRB 2 event is not logged by the SMI handler but it will use the same generator ID ra...

Page 141: ...g initialized Operation represents the specific initialization activity Based on the data bit availability to display the progress code a progress code can be customized to fit the data width The higher the data bit higher the granularity of allowable information Progress codes may be reported by system BIOS or option ROMs The response section in the following table is divided into three types War...

Page 142: ... 004E Primary Slave Hard Disk Error Pause 004F Secondary Master Hard Disk Error Pause 0050 Secondary Slave Hard Disk Error Pause 0055 Primary Master Drive ATAPI Incompatible Pause 0056 Primary Slave Drive ATAPI Incompatible Pause 0057 Secondary Master Drive ATAPI Incompatible Pause 0058 Secondary Slave Drive ATAPI Incompatible Pause 0059 Third Master Device Error Pause 005B Fourth Master Device Er...

Page 143: ...ed BIST Pause 8171 Processor 02 failed BIST Pause 8180 BIOS does not support current stepping for Processor 1 Pause 8181 BIOS does not support current stepping for Processor 2 Pause 8190 Watchdog timer failed on last boot Warning 8198 OS boot watchdog timer failure Pause 8300 Baseboard Management Controller failed Self Test Pause 8301 Not enough space in Runtime area SMBIOS data will not be availa...

Page 144: ...nt in flash device 1 long beep Insert diskette with AMIBOOT 001 file for multi disk recovery 6 2 3 POST Error Beep Codes The following table lists the POST error beep codes Before system video initialization the BIOS uses these beep codes to inform users of error conditions Table 62 POST Error Beep Codes Number of Beeps Description 1 Memory refresh timer error 2 Parity error in base memory first 6...

Page 145: ... Pause to disabled in the BIOS setup Advanced menu page If the POST Error Pause option is set to disabled the system will boot the operating system without user intervention The default value setting for this option is enabled 6 3 Checkpoints 6 3 1 System ROM BIOS POST Task Test Point Port 80h Code The BIOS sends a 1 byte hex code to port 80 before each task The port 80 codes provide a troubleshoo...

Page 146: ...per nibble and the green bits correspond to the lower nibble the two are concatenated to be ACh Table 64 POST Progress Code LED Example LEDs Red Green Red Green Red Green Red Green Ach 1 1 0 1 1 0 0 0 Result Amber Green Red Off MSB LSB Figure 18 Location of Diagnostic LEDs Example only LSB MSB Diagnostic LEDs Back edge of server ...

Page 147: ...em timer interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock 08 G OFF OFF OFF Initializes the CPU The BAT test is being done on KBC Program the keyboard controller command byte is being done after Auto detection of KB MS using AMI KB 5 C0 R R OFF OFF Early CPU Init Start Disable Cache Init Local APIC C1 R R OFF G Set up boot strap processor Information C2 R R G OFF Set up boot strap processor ...

Page 148: ... and update the BDA EBDA etc 50 OFF R OFF R Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed 52 OFF R G R Updates CMOS memory size from memory found in memory test Allocates memory for Extended BIOS Data Area from base memory 60 OFF R R OFF Initializes NUM LOCK status and programs the KBD typematic rate 75 OFF A R A Initialize Int 13 a...

Page 149: ...ion Before D1 Early chipset initialization is done Early super I O initialization is done including RTC and keyboard controller NMI is disabled D1 R R OFF A Perform keyboard controller BAT test Check if waking up from power management suspend state Save power on CPUID value in scratch CMOS D0 R R OFF R Go to flat mode with 4 GB limit and GA20 enabled Verify the bootblock checksum D2 R R G R Disabl...

Page 150: ... the floppy controller in the super I O Some interrupt vectors are initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled E9 A R R G Set up floppy controller and data Attempt to read from floppy Determine information about root directory of recovery media EA A R A OFF Enable ATAPI hardware Attempt to read from ARMD and ATAPI CD ROM Determine informat...

Page 151: ...tatic resources are also reserved Boot Output Device Initialization function 2 Function 2 searches for and initializes any PnP PCI or AGP video devices 38 Initialize different buses and perform the following functions Boot Input Device Initialization function 3 Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller IPL Device Initialization ...

Page 152: ...S 0EAh MEM_ERR_TIMING 0EBh MEM_ERR_INST_ORDER_ERR 0ECh MEM_ERR_NONREG_MIX 0EDh MEM_ERR_LATENCY 0EEh MEM_ERR_NOT_SUPPORTED 0EFh MEM_ERR_CONFIG_NOT_SUPPORTED 0F0h SYS_FREQ_ERR Flag for Unsupported System Bus Freq 0F1h DIMM_ERR_CFG_MIX Usupported DIMM mix 0F2h DQS_FAILURE indicates DQS failure 0F3h MEM_ERR_MEM_TEST_FAILURE Error code for unsuccessful Memory Test 0F4h MEM_ERR_ECC_INIT_FAILURE Error co...

Page 153: ... Pin Signal 18 AWG Color 1 3 3VDC Orange 13 3 3VDC Orange 3 3V RS Orange 24AWG 14 12VDC Blue 2 3 3VDC Orange 15 COM Black 3 COM Black 16 PSON Green COM RS Black 24AWG 17 COM Black 4 5VDC Red 18 COM Black 5V RS Red 24AWG 19 COM Black 5 COM Black 20 Reserved N C 6 5VDC Red 21 5VDC Red 7 COM Black 22 5VDC Red 8 PWR OK Gray 23 5VDC Red 9 5 VSB Purple 24 COM Black 10 12V3 Yellow 11 12V3 Yellow 12 3 3VD...

Page 154: ... CS0 5 DQS0 36 DQS3 66 VSS 97 DM0 128 VDDQ 158 CS1 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DM3 159 DM5 7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 RESET 41 A2 71 CS2 102 NC 133 DQ31 163 CS3 11 VSS 42 VSS 72 DQ48 103 A13 134 CB4 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52 13 DQ9 44 CB0 74 VSS 105 DQ12 1...

Page 155: ...in Name Pin No Pin Name A1 VID5 D29 VCC K3 VCC T29 VSS AB3 2 BSEL1 A2 VCC D30 VSS K4 VSS T30 VCC AB4 VCCA A3 SKTOCC D31 VCC K5 VCC T31 VSS AB5 VSS A4 VTT E1 VTTEN K6 VSS U1 VCC AB6 D63 A5 VSS E2 VCC K7 VCC U2 VSS AB7 PWRGOOD A6 A32 E3 VID1 K8 VSS U3 VCC AB8 VCC A7 A33 E4 BPM5 K9 VCC U4 VSS AB9 DBI3 A8 VCC E5 IERR K23 VCC U5 VCC AB10 D55 A9 A26 E6 VCC K24 VSS U6 VSS AB11 VSS A10 A20 E7 BPM2 K25 VCC...

Page 156: ...1 B11 A22 F8 BPM1 M8 VSS W3 Reserved AC13 VSS B12 VTT F9 GTLREF M9 VCC W4 VSS AC14 D50 B13 A13 F10 VTT M23 VCC W5 BCLK1 AC15 DP2 B14 A12 F11 BINIT M24 VSS W6 TESTHI0 AC16 VCC B15 VSS F12 BR1 M25 VCC W7 TESTHI1 AC17 D34 B16 A11 F13 VSS M26 VSS W8 TESTHI2 AC18 DP0 B17 VSS F14 ADSTB1 M27 VCC W9 GTLREF AC19 VSS B18 A5 F15 A19 M28 VSS W23 GTLREF AC20 D25 B19 REQ0 F16 VCC M29 VCC W24 VSS AC21 D26 B20 VC...

Page 157: ...20 REQ3 G30 VCC P25 VSS Y25 VSS AD22 DBI1 C21 REQ2 G31 VSS P26 VCC Y26 D0 AD23 VSS C22 VCC H1 VCC P27 VSS Y27 THERMDA AD24 D21 C23 DEFER H2 VSS P28 VCC Y28 THERMDC AD25 D18 C24 TDI H3 VCC P29 VSS Y29 NC AD26 VCC C25 VSS H4 VSS P30 VCC Y30 VCC AD27 D4 C26 IGNNE H5 VCC P31 VSS Y31 VSS AD28 NC C27 SMI H6 VSS R1 VCC AA1 VCC AD29 NC C28 VCC H7 VCC R2 VSS AA2 VSS AD30 VCC C29 VSS H8 VSS R3 VCC AA3 BSEL0...

Page 158: ...D28 VSS K2 VSS T28 VCC AB2 VCC Notes 1 These are Reserved pins on the Intel Xeon processor In systems utilizing the Intel Xeon processor the system designer must terminate these signals to the processor VTT 2 Server boards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 200 MHz 3 The FC mPGA2P package contains an extra pin located at location AE30 compared to the INT mP...

Page 159: ...out for each segment is below Table 79 P32 A 5V 32 bit 33 MHz PCI Slot Pin out J10 J11 Pin Side B Side A Pin Side B Side A 1 12V TRST 32 AD 17 AD 16 2 TCK 12V 33 C BE 2 3 3V 3 Ground TMS 34 Ground FRAME 4 TDO TDI 35 IRDY Ground 5 5V 5V 36 3 3V TRDY 6 5V INTA 37 DEVSEL Ground 7 INTB INTC 38 Ground STOP 8 INTD 5V 39 LOCK 3 3V 9 PRSNT1 Reserved 40 PERR SMBCLK 10 Reserved 5V I O 41 3 3V SMBDAT 11 PRSN...

Page 160: ...52 AD 08 C BE 0 5 5V 5V 53 AD 07 3 3V 6 5V INTA 54 3 3V AD 06 7 INTB INTC 55 AD 05 AD 04 8 INTD 5V 56 AD 03 Ground 9 PRSNT1 Reserved 57 Ground AD 02 10 Reserved 3 3V I O 58 AD 01 AD 00 11 PRSNT2 Reserved 59 3 3V I O 3 3V I O 12 CONNECTOR KEY 60 ACK64 REQ64 13 CONNECTOR KEY 61 5V 5V 14 Reserved 3 3Vaux 62 5V 5V 15 Ground RST CONNECTOR KEY 16 CLK 3 3V I O CONNECTOR KEY 17 Ground GNT 63 Reserved Grou...

Page 161: ...9 AD 35 AD 34 44 C BE 1 AD 15 90 AD 33 Ground 45 AD 14 3 3V 91 Ground AD 32 46 Ground AD 13 92 Reserved Reserved 47 AD 12 AD 11 93 Reserved Ground 48 AD 10 Ground 94 Ground Reserved Table 81 PCI Express Slot Pin out J13 for x4 J14 for x16 Pin Side B Side A Pin Side B Side A 1 12V PRSNT1 42 HSION6 GND 2 12V 12V 43 GND HSIP6 3 RSVD 12V 44 GND HSIN6 4 GND GND 45 HSOP7 GND 5 SMCLK TCK 46 HSON7 GND 6 S...

Page 162: ...11 24 HSON2 GND 65 GND HSIN11 25 GND HSIP2 66 HSOP12 GND 26 GND HSIN2 67 HSON12 GND 27 HSOP3 GND 68 GND HSIP12 28 HSON3 GND 69 GND HSIN12 29 GND HSIP3 70 HSOP13 GND 30 RSVD HSIN3 71 HSON13 GND 31 PRSNT 2 GND 72 GND HSIP13 32 GND RSVD 73 GND HSIN13 End of the x4 Connector 33 HSOP4 RSVD 74 HSOP14 GND 34 HSON4 GND 75 HSON14 GND 35 GND HSIP4 76 GND HSIP14 36 GND HSIN4 77 GND HSIN14 37 HSOP5 GND 78 HSO...

Page 163: ...er Pin out J38 Signal Name Pin Pin Signal Name ACPI_LEDgrn 1 2 SB5V KEY 3 4 FAN_FAULT LED NO SUPPORT 1 ACPI_LED amber 5 6 FAN_FAULT LED NO SUPPORT 1 HDD_LED 7 8 SYS_Status LED 2 HDD_LED 9 10 SYS_Status LED PWR_BTN 11 12 NIC1 ACT_LED PWR_BTN GND 13 14 NIC1 ACT_LED RESET switch 15 16 SMB SDA RESET switch GND 17 18 SMB SCL Sleep switch NO SUPPORT 1 19 20 INDRUDER 1 Sleep switch GND 1 21 22 NIC2 ACT_L...

Page 164: ...4 Signal Name Pin Pin Signal Name RED B1 B9 Fused VCC 5V NO SUPPORT GREEN B2 B10 NC BLUE B3 B11 NC NC B4 B12 DDCDAT GND B5 B13 HSY GND B6 B14 VSY GND B7 B15 DDCCLK GND B8 B16 NC B17 NC Note NC No Connect t 7 8 NIC Connector Table 84 NIC1 82541GI 10 100 1000 Connector Pin out JA1 Signal Name Pin Pin Signal Name GND 1 9 MDI_3N MDI_2N 2 10 MDI_0N MDI_2P 3 11 MDI_0P MDI_1P 4 12 GND MDI_1N 5 13 ACT_L G...

Page 165: ...IDE_DD9 7 IDE_DD5 8 IDE_DD10 9 IDE_DD4 10 IDE_DD11 11 IDE_DD3 12 IDE_DD12 13 IDE_DD2 14 IDE_DD13 15 IDE_DD1 16 IDE_DD14 17 IDE_DD0 18 IDE_DD15 19 GND 20 KEY 21 IDE_DMAREQ 22 GND 23 IDE_IOW 24 GND 25 IDE_IOR 26 GND 27 IDE_IORDY 28 GND 29 IDE_DMAACK 30 GND 31 IRQ_IDE 32 Test Point 33 IDE_A1 34 DIAG 35 IDE_A0 36 IDE_A2 37 IDE_DCS0 38 IDE_DCS1 39 IDE_HD_ACT 40 GND 7 10 SATA Connectors Table 86 SATA Co...

Page 166: ...C 5V w over current monitor of both port 2 6 DATAN2 Differential data line paired with DATAH2 7 DATAP2 Differential data line paired with DATAL2 8 GND 9 CTS_N 10 DSR_DCD 11 SIN 12 RI_N 13 GND 14 SIUT 15 DTR_N 16 RTS_N A header on the server board provides an option to support one additional USB connector The pin out of the header is detailed in the following table Table 88 Optional USB Connection ...

Page 167: ...etail the pin out of the 34 pin floppy connector Table 89 Legacy 34 pin Floppy Connector Pin out J47 Signal Name Pin Pin Signal Name GND 1 2 FDDENSEL GND 3 4 Unused KEY 5 6 FDDRATE0 GND 7 8 FDINDEX GND 9 10 FDMTR0 GND 11 12 FDR1 GND 13 14 FDR0 GND 15 16 FDMTR1 Unused 17 18 FDDIR GND 19 20 FDSTEP GND 21 22 FDWDATA GND 23 24 FDWGATE GND 25 26 FDTRK0 Unused 27 28 FLWP GND 29 30 FRDATA GND 31 32 FHDSE...

Page 168: ...port is provided through a 9 pin header J15 on the server board The following tables detail the pin outs of these two ports Table 90 External DB9 Serial A Port Pin out J8A1 Signal Name Pin Pin Signal Name SERIAL_DCD1_FB T1 T6 SERIAL_DSR1_FB SERIAL_RX1_FB T2 T7 SERIAL_RTS1_FB SERIAL_TX1_FB T3 T8 SERIAL_CTS1_FB SERIAL_DTR1_FB T4 T9 SERIAL_RING1_FB GND T5 Table 91 9 pin Header Serial B Port Pin out J...

Page 169: ...d 6 NC 7 MSEDATA 8 NC 9 GND 10 KMPWR 11 MSECLK Mouse 12 13 14 15 16 17 GND 7 15 Miscellaneous Headers 7 15 1 Fan Header There are six 3 pin fan headers All fan headers provide speed monitoring onboard The fan headers are labeled CPU_1 FAN and CPU_2 FAN and SYS FAN_1 4 All fan headers have the same pin out and are detailed below Table 93 Three pin Fan Headers Pin out J51 J52 J7 J1 J45 J48 Pin Signa...

Page 170: ...er Fan Power 3 Fan Tach Out FAN_TACH signal is connected to the Super I O to monitor the FAN speed 4 Fan PWM Out Fan speed control 5 N C 6 N C 7 15 2 Intrusion Cable Connector Table 95 Intrusion Cable Connector J19 Pin out Pin Signal Name 1 INTRUDER_N 2 GND 7 15 3 SCSI LED Header Table 96 SCSI LED Header Pin out J26 Pin Signal Name Description 1 GND Ground 2 SCSI_CONN_LED_N Activity Signal 3 SCSI_...

Page 171: ...h jumper option Table 97 Configuration Jumper Options Option Description CMOS Clear If pins 1 and 2 are jumpered default preservation of configuration CMOS through system reset is controlled by the mBMC If pins 2 and 3 are jumpered CMOS contents are set to manufacturing default during system reset Password Clear If pins 1 and 2 are jumpered default the current BIOS Setup Utility passwords are main...

Page 172: ...on to force the board to boot from Bank 0 as part of the Rolling BIOS feature The figure below shows the factory default location for the jumper option Figure 20 BIOS Bank Jumper J26 The following table describes the jumper option Table 98 BIOS Bank Jumper Option Option Description Auto If pins 1 and 2 are jumpered default the platform instrumentation on the board controls which BIOS bank has the ...

Page 173: ...erature VDD means supply voltage for the device Note Intel Corporation server boards contain a number of high density VLSI and power delivery components which need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components ...

Page 174: ... should be used 8 4 Power Supply Specifications This section provides power supply design guidelines for an system using either server board including voltage and current specifications and power supply on off sequencing characteristics Table 102 Power Supply Voltage Specification Output Min Max Tolerance 3 3 V 3 14 V 3 46 V 5 5 5 V 4 75 V 5 25 V 5 5 12 V 11 40 V 12 60 V 5 5 12 V 11 40 V 13 08 V 5...

Page 175: ...ON held low and the PSON signal with the AC input applied The ACOK signal is not being used to enable the turn on timing of the power supply Table 103 Voltage Timing Parameters Item Description Min Max Units Tvout_rise Output voltage rise time from each main output 5 70 msec Tvout_on All main outputs must be within regulation of each other within this time 50 msec T vout_off All main outputs must ...

Page 176: ...n_delay Delay from PSON active to output voltages within regulation limits 5 400 msec T pson_pwok Delay from PSON deactive to PWOK being de asserted 50 msec Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on 100 1000 msec T pwok_off Delay from PWOK de asserted to output voltages 3 3V 5V 12V 12V dropping out of regulation limits 1 200 msec Tpwok_low Duration of...

Page 177: ... Revision 4 0 165 Figure 22 Turn On Off Timing AC Input Vout PWOK 5VSB PSON Tsb_on_delay TAC_on_delay Tpwok_on Tvout_holdup Tpwok_holdup Tpson_on_delay Tsb_on_delay Tpwok_on Tpwok_off Tpwok_off Tpson_pwok Tpwok_low Tsb_vout AC turn on off cycle PSON turn on off cycle ...

Page 178: ...tire AC input range and any steady state temperature and operating conditions specified Voltages shall be stable as determined by bode plot and transient response The combined error of peak overshoot set point regulation and undershoot voltage shall be less than or equal to 5 of the output voltage setting The transient response measurements shall be made with a load changing repetition rate of 50 ...

Page 179: ...r boards have been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed in a compatible Intel host system For information on compatible host system s contact your local Intel representative FCC ICES 003 Verification to Class A Emissions USA Canada CISPR 22 Class A Emissions International EN55022 Class A Emissions CENELEC Europe EN55024 Immun...

Page 180: ...t be list on System Level GOST license Alternatively you can obtain voluntary GOST certification for the board 9 1 3 Product Regulatory Compliance Markings This product is provided with the following Product Certification Markings cURus Recognition Mark CE Mark Russian GOST Mark Australian C Tick Mark Korean RRL MIC Mark Taiwan BSMI Certification Number R33025 and BSMI EMC Warning 9 2 Electromagne...

Page 181: ...r customer service representative or dealer for a list of approved devices WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer Discard used batteries according to manufacturer s instructions ADVARSEL Lithiumbatteri Eksplosionsfare ved fejlagtig håndtering Udskiftning må kun ske med batteri af samme f...

Page 182: ......

Page 183: ...tel Server Chassis SC5300 Base Sys Fan 2 and Sys Fan 3 are used when integrating the server board in the Intel Entry Server Chassis SC5275 E When integrating Intel Server Boards SE7320SP2 or SE7525GP2 into the Intel Server Chassis SC5300 the system utilizes the 2U passive no fan heatsink solution of the Intel Xeon processor If you are integrating either of these server boards into the Intel Entry ...

Page 184: ...ower Interface BMC Baseboard Management Controller CEK Common Enabling Kit CME Correctable Memory Error DVI Digital Video Interface FML Fast Management Link FMM Flexible Management Module FSB Front Side Bus KCS Keyboard Controller Style LPC Low Pin Count mBMC Mini Baseboard Management Controller MCH Memory Controller Hub NMI Non maskable Interrupt PATA Parallel ATA PCB Printed Circuit Board PWM Pu...

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