Intel SE7320SP2 - 800MHZ Ecc Ddr Xeon, Technical Manual

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Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling
Revision 4.0 135
6.3.3 POST Code Checkpoints
Table 65. POST Code Checkpoints
Diagnostic LED Decoder
G=Green, R=Red, A=Amber Checkpoint
MSB LSB
Description
03 OFF OFF G G
Disable NMI, parity, video for EGA, and DMA controllers. Initialize
BIOS, POST, Run-time data area. Initialize BIOS modules on POST
entry and GPNV area. Initialized CMOS as mentioned in the Kernel
Variable "wCMOSFlags."
04 OFF G OFF OFF
Check CMOS diagnostic byte to determine if battery power is OK
and CMOS checksum is OK. Verify CMOS checksum manually by
reading storage area. If the CMOS checksum is bad, update CMOS
with power-on default values and clear passwords. Initialize status
register A.
Initializes data variables that are based on CMOS setup questions.
Initializes both the 8259 compatible PICs in the system
05 OFF G OFF G
Initializes the interrupt controlling hardware (generally PIC) and
interrupt vector table.
06 OFF G G OFF
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer.
Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system
timer interrupt.
Traps INT1Ch vector to "POSTINT1ChHandlerBlock."
08 G OFF OFF OFF
Initializes the CPU. The BAT test is being done on KBC. Program the
keyboard controller command byte is being done after Auto detection
of KB/MS using AMI KB-5.
C0 R R OFF OFF Early CPU Init Start -- Disable Cache - Init Local APIC
C1 R R OFF G Set up boot strap processor Information
C2 R R G OFF Set up boot strap processor for POST
C5 R A OFF G Enumerate and set up application processors
C6 R A G OFF Re-enable cache for boot strap processor
C7 R A G G Early CPU Init Exit
0A G OFF G OFF Initializes the 8042 compatible Key Board controller.
0B G OFF G G Detects the presence of PS/2 mouse.
0C G G OFF OFF Detects the presence of Keyboard in KBC port.
0E G G G OFF
Testing and initialization of different Input Devices. Also, update the
Kernel Variables.
Traps the INT09h vector, so that the POST INT09h handler gets
control for IRQ1. Uncompress all available language, BIOS logo, and
Silent logo modules.
13 OFF OFF G A Early POST initialization of chipset registers.
24 OFF G R OFF Uncompress and initialize any platform specific BIOS modules.
30 OFF OFF R R Initialize System Management Interrupt.
2A G OFF A OFF
Initializes different devices through DIM.
See DIM Code Checkpoints section of document for more
information.