Platform Management
Intel® Server Boards SE7320SP2 and SE7525GP2
Revision
4.0
104
5.2.4.4
Host to mBMC Communication Interface
The host communicates with the mBMC via the System Management Bus (SMBus). The
interface consists of three signals:
SMBus clock signal (SCLH)
SMBus data signal (SDAH)
Optional SMBus alert signal (SMBAH). The signal notifies the host that the PC87431x
has data to provide.
The mBMC is a slave device on the bus. The host interface is designed to support polled
operations. Host applications can optionally handle an SMBus alert interrupt if the mBMC is
unable to respond immediately to a host request. In this case, “Not Ready” is indicated in one of
two ways:
The host interface bandwidth is limited by the bus clock and mBMC latency. To meet the
device latency, the mBMC slows down the bus periodically by extending the SMBus
clock low interval (SCLH).
If the mBMC is in the middle of a LAN or peripheral device communication, or if a
response to the host request is not yet ready, the mBMC does not acknowledge the
device address (“NAK”). This forces the host software to stop and restart the session.
For more information on read-write through SMBus, see the
System Management Bus
(SMBus)
Specification 2.0.
5.2.4.5 LAN
Interface
The server board supports one DPC LAN interface via a UDP port 26Fh. The mBMC supports a
maximum of one simultaneous session across all authenticated channels. The server board
implements gratuitous ARP support according to the IPMI 1.5 Specification.
The IPMI Specification v1.5 defines how IPMI messages, encapsulated in RMCP packet format,
can be sent to and from the mBMC. This capability allows a remote console application to
access the mBMC and perform the following operations:
Chassis control, e.g., get chassis status, reset chassis, power-up chassis, power-down
chassis
Get system sensor readings
Get and Set system boot options
Get Field Replaceable Unit (FRU) information
Get System Event Log (SEL) entries
Get Sensor Data Records (SDR)
Set Platform Event Filtering (PEF)
Set LAN configurations
Summary of Contents for SE7320SP2 - 800MHZ Ecc Ddr Xeon
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