Functional Architecture
Intel® Server Boards SE7320SP2 and SE7525GP2
Revision
4.0
22
3.4.10
Enhanced Power Management
The Intel
®
6300ESB I/O controller power management functions include enhanced clock control,
local and global monitoring support for 14 individual devices, and various low-power (suspend)
states (e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management
circuit permits software-independent entrance to low-power states. The Intel 6300ESB I/O
controller contains full support for the Advanced Configuration and Power Interface (ACPI)
Specification, Revision 2.0b.
3.4.11
System Management Bus (SMBus 2.0)
The Intel
®
6300ESB I/O controller contains an SMBus Host interface that allows the processor
to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special
I2C commands are implemented. The Intel 6300ESB I/O controller SMBus host controller
provides a mechanism for the processor to initiate communications with SMBus peripherals
(slaves). Also, the Intel 6300ESB I/O controller supports slave functionality, including the Host
Notify protocol. Hence, the host controller supports eight command protocols of the SMBus
interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write,
and Host Notify.
3.5 Memory
Sub-System
The MCH provides an integrated memory controller for direct connection to two channels of
registered DDR266 or DDR333 memory (stacked or unstacked). Peak theoretical memory data
bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/s for DDR333 technology.
When both DDR channels are populated and operating, they function in lock-step mode. The
maximum supported memory size for either memory speed is 8 GB.
The MCH supports a burst length of four whether in single or dual-channel mode. In dual-
channel mode this results in eight 64-bit chunks (64-byte cache line) from a single read or write.
In single-channel mode two reads or writes are required to access a cache line of data.
3.5.1 Memory
Sizing
The server boards provide four DDR266 / DDR333 DIMM sites. There are two DIMM sites on
each memory channel.
DIMMs on channel A are paired with DIMMs on channel B to configure 2-way interleaving. The
minimum memory configuration to support interleaving is two DIMMs, which requires same
DIMM populated from each channel. Each board does support single-channel memory
operation with a single DIMM populated in DIMM location 1 on either bank (1A or 2A). It should
be noted that single-channel operation greatly reduces memory bandwidth and RAS
capabilities.
Memory DIMM technologies supported are: 128 Mb, 256 Mb, 512 Mb, 1 Gb and 2 Gb.
Physical DIMM sizes supported are 256 MB, 512 MB, 1 GB, and 2 GB.
Summary of Contents for SE7320SP2 - 800MHZ Ecc Ddr Xeon
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