Intel PXA270, Optimization Manual

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4-24 Intel® PXA27x Processor Family Optimization Guide
Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
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Multi-cycles may be interleaved with other instructions
The C-code for the N-Sample, T-Tap block FIR filter is also used to illustrate the multi-sample
technique.
for (i = 0; i < N; i++4) {
s0=s1=s2=s3=0;
for (j = 0; j < T/4; j++4) {
s0 += a[j]*x[i-j];
s1 += a[j]*x[i-j+1];
s2 += a[j]*x[i-j+2];
s3 += a[j]*x[i-j+3]);
}
y[i] = round (s0);
y[i+1] = round (s1);
y[i+2] = round (s2);
y[i+3] = round (s3);
}
In the inner loop, we are calculating four output samples using the adjacent data samples x(n-i) ,
x(n-1+1) , x(n-i+2) and x(n-i+3). The output samples y(n) , y(n+1) , y(n+2) , and y(n+3) are assigned
to four 64-bit Intel® Wireless MMX™ Technology registers. In order to obtain near ideal
throughput, the inner loop is unrolled to provide for eight taps for each of the four output samples
per loops iteration.
; ** Update pointers,
Outer_Loop:
; ** Update pointers,zero accumulators and prime the loop with DWORD loads
WLDRD wR0, [R1], #8 ; Load first 4 input samples
WZERO wR15
WLDRD wR1, [R1], #8 ; Load even groups of 4
; input samples
WZERO wR14
WLDRD wR8, [R2], #8; Load first 4 coefficients
WZERO wR13
WZERO wR12
InnerLoop:
; ** Executes 8-Taps for each four outputs samples
; y(n),y(n+1), y(n+2),y(n+3)
SUBS R0 ,R0 , #8 ; Decrement loop counter
WMAC wR15,wR8 , wR0 ; y(n)+=
WALIGNI wR3 ,wR1 , wR0, #2
WMAC wR14,wR8 , wR3 ; y(n+1) +=
WALIGNI wR3 ,wR1 , wR0, #4
WMAC wR13,wR8 , wR3 ; y(n+2) +=
WLDRD wR0, [R1], #8 ;next 4 input samples
WALIGNI wR3 ,wR1 , wR0, #6
WLDRD wR9, [R2], #8 ; odd groups of 4 coeff.
WMAC wR12,wR8 , wR3 ; y(n+3) +=