1-4
Intel® PXA27x Processor Family
Optimization Guide
Introduction
1.2.2
Intel XScale® Microarchitecture Features
•
Superpipelined RISC technology achieves high speed and low power
•
Wireless Intel Speedstep® technology allows on-the-fly voltage and frequency scaling to
enable applications to use the right blend of performance and power
•
Media processing technology enables the MAC coprocessor perform two simultaneous 16-bit
SIMD multiplies with 64-bit accumulation for efficient media processing
•
Power management unit provides power savings via multiple low-power modes
•
128-entry Branch Target buffer keeps pipeline filled with statistically correct branch choices
•
32-Kbyte instruction cache (I-cache) keeps local copy of important instructions to enable high
performance and low power
•
32-Kbyte data cache (D-cache) keeps local copy of important data to enable high performance
and low power
•
2-Kbyte mini-data cache avoids “thrashing” of the D-cache for frequently changing data
streams
•
32-entry instruction memory management unit enables logical-to-physical address translation,
access permissions, I-cache attributes
•
32-entry data memory management unit enables logical-to-physical address translation, access
permissions, D-cache attributes
•
4-entry Fill and Pend buffers promote core efficiency by allowing “hit-under-miss” operation
with data caches
•
Performance monitoring unit furnishes two 32-bit event counters and one 32-bit cycle counter
for analysis of hit rates
•
Debug unit uses hardware breakpoints and 256-entry Trace History buffer (for flow change
messages) to debug programs
•
32-bit coprocessor interface provides high performance interface between core and
coprocessors
•
8-entry Write buffer allows the core to continue execution while data is written to memory
See the
Intel XScale® Microarchitecture Users Guide
for additional information.
1.2.3
Intel® Wireless MMX™ technology
The Intel XScale® Microarchitecture has attached to it a coprocessor to accelerate multimedia
applications. This coprocessor, characterized by a 64-bit Single Instruction Multiple Data (SIMD)
architecture and compatibility with the integer functionality of the Intel® Wireless MMX™
technology and SSE instruction sets, is known by its Intel project name, Intel® Wireless MMX™
technology. The key features of this coprocessor are:
•
30 new media processing instructions
•
64-bit architecture up to eight-way SIMD
•
16 x 64-bit register file
•
SIMD PSR flags with group conditional execution support
•
Instruction support for SIMD, SAD, and MAC
•
Instruction support for alignment and video
•
Intel® Wireless MMX™ technology and SSE integer compatibility
Summary of Contents for PXA270
Page 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Page 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Page 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Page 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Page 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Page 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Page 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Page 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
Page 144: ......
