Intel PXA270, Optimization Manual

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Intel® PXA27x Processor Family Optimization Guide 4-47
Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.10.2.2 Multiply Pipeline
Instructions issued to the multiply pipeline may take up to two cycles before another instruction
can be issued to the pipeline. The instructions in the multiply pipe can be categorized into 4 classes
shown in Table 4-20 . The resource-availability delay for the instructions that are mapped onto the
multiplier pipeline depend upon the class of the multiply instruction that subsequently wants to use
the multiply resource. These delays for are shown below in
Table 4-21 . For example if a TMIA
instruction is followed by a TMIAph (class3) instruction, then the TMIAph sees a resource
availability of 2 cycles.
WAVG2 1
WMAX 1
WMIN 1
WSAD 1
†
WSLL 1
WSRA 1
WSRL 1
WROR 1
WPACK 1
WUNPCKEH 1
WUNPCKEL 1
WUNPCKIH 1
WUNPCKIL 1
WALIGNI 1
WALIGNR 1
WSHUF 1
TMIA 1
†
TMIAph 1
†
TMIAxy 1
†
TMCR 1
TMCRR 1
TINSR 1
TBCST 1
TANDC 1
TORC 1
TEXTRC 1
† The WSAD, TMIA, TMIAph, TMIAxy execute in both the
main execution pipeline and the multiplier pipeline. They
execute for one cycle in the execution pipeline and the
rest in the multiplier pipeline. See Section 4.10.2.5 for
more details
Table 4-19. Resource Availability Delay for the Execution Pipeline (Sheet 2 of 2)
Instructions Delay (Clocks)