Intel PXA270, Optimization Manual

Page: 85 / 144

Intel® PXA27x Processor Family Optimization Guide 4-37
Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Table 4-2 shows how to calculate issue latency and result latency for each instruction. The
UMLAL instruction (shown in the issue column) starts to issue on cycle 0 and the next instruction,
ADD, issues on cycle 2, so the issue latency for UMLAL is two. From the code fragment, there is a
result dependency between the UMLAL instruction and the SUB instruction. In
Table 4-2 ,
UMLAL starts to issue at cycle 0 and the SUB issues at cycle 5, thus the result latency is five.
4.8.2 Branch Instruction Timings
(
Table 4-2. Latency Example
Cycle Issue Executing
0 umlal (1st cycle) —
1 umlal (2nd cycle) umlal
2 add umlal
3 sub (stalled) umlal & add
4 sub (stalled) umlal
5 sub umlal
6 mov sub
7 — mov
Table 4-3. Branch Instruction Timings (Those Predicted By the BTB (Branch Target Buffer))
Instruction
Minimum Issue Latency When Correctly
Predicted By The Btb
Minimum Issue Latency With Branch
Misprediction
B 1 5
BL 1 5
Table 4-4. Branch Instruction Timings (Those Not Predicted By the BTB)
Instruction
Minimum Issue Latency When
the Branch Is Not Taken
Minimum Issue Latency When
the Branch is Taken
BLX(1) — 5
BLX(2) 1 5
BX 1 5
Data Processing Instruction with
PC as the destination
Same as Table 4-5 4 + numbers in Table 4-5
LDR PC,<> 2 8
LDM with PC in register list 3 + numreg
†
10 + max (0, numreg-3)
† numreg is the number of registers in the register list including the PC.