Intel® PXA27x Processor Family
Optimization Guide
6-5
Power Optimization
6.3
Optimizations for Memory and Peripheral Power
This section lists optimizations that may help to reduce power consumption primarily by the
memory and peripheral subsystems. Using hardware that supports lower voltages such as 1.8 V
SDRAM flash is a key factor.
6.3.1
Improved Caching and Internal Memory Usage
Transactions to the external memory are the largest contributors to the system’s power
consumption. Reducing external memory transactions, by improving the cache efficiency and
internal-SRAM efficiency reduces the power consumption.
6.3.2
SDRAM Auto Power Down (APD)
The APD bit is a setting in the memory controller’s MDREFR register that allows the clock-enable
and clocks to SDRAM or synchronous static memory to be automatically disabled when not used.
When the memory does need to be accessed, an additional latency of one clock occurs to re-enable
the clock signals.
Enabling APD is useful during periods of system inactivity, such as the idle loop. During periods of
system activity, users need to weigh the additional power savings with APD against the additional
latency incurred.
6.3.3
External Memory Bus Buffer Strength Registers
The output drivers for the PXA27x processor external-memory bus have programmable-strength
settings. This feature allows for simple, software-based control of the output-driver impedance for
the external-memory bus. Use these registers to match the driver strength of the PXA27x processor
to external-memory bus. The buffer strength should be set to the lowest possible setting (minimum
drive strength) that still allows for reliable memory-system performance. This minimizes the power
usage of the external memory bus, which is a major component of total system power. Refer to the
Programmable Output Buffer Strength registers in the
Intel® PXA27x Processor Family
Developer’s Manual
for more information.
6.3.4
Peripheral Clock Gating
If peripherals are not used, their clocks can be disabled to save power. The CKEN register in the
clocks manager contain configuration bits that control the clocks to each peripheral. To save power,
users should disable unneeded peripherals.
6.3.5
LCD Subsystem
The LCD subsystem, which consists of the LCD panel, power supplies, and backlight, can be
optimized to reduce system power. Lowering the refresh rate of the LCD panel reduces power used
by the memory bus. This can be done dynamically by monitoring the system inactivity and
lowering the refresh rate accordingly. If the LCD has a backlight, disabling it after a short time
further reduces power. Software can disable the LCD during long periods of inactivity and enter
sleep mode.
Summary of Contents for PXA270
Page 1: ...Order Number 280004 001 Intel PXA27x Processor Family Optimization Guide April 2004...
Page 10: ...x Intel PXA27x Processor Family Optimization Guide Contents...
Page 20: ...1 10 Intel PXA27x Processor Family Optimization Guide Introduction...
Page 30: ...2 10 Intel PXA27x Processor Family Optimization Guide Microarchitecture Overview...
Page 48: ...3 18 Intel PXA27x Processor Family Optimization Guide System Level Optimization...
Page 114: ...5 16 Intel PXA27x Processor Family Optimization Guide High Level Language Optimization...
Page 122: ...6 8 Intel PXA27x Processor Family Optimization Guide Power Optimization...
Page 143: ...Intel PXA27x Processor Family Optimization Guide Index 5 Index...
Page 144: ......
