Intel PXA270, Optimization Manual

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Intel® PXA27x Processor Family Optimization Guide 1-9
Introduction
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PID register for fast virtual address remapping
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Vector remap
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Interrupt controller offers faster interrupt latency with the help of programmable priority
sorting mechanism.
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Extensions to the exception model to include imprecise data and instruction preload aborts
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Access control to other coprocessors
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Enhanced set of supported cache-control options
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A branch target buffer for dynamic-branch prediction
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Performance monitoring unit
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Software-debug support, including instruction and data breakpoints, a serial debug link via the
JTAG interface and a 256-entry trace buffer
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Integrated memory controller with support for SDRAM, flash memory, synchronous ROM,
SRAM, variable latency I/O (VLIO) memory, PC card, and compact flash expansion memory.
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Six power-management modes